Abstract: An apparatus for controlling the transmission of multiple level priority interrupt signals to a central processing unit. A number of storage elements are responsive to the interrupt signals on an individual basis. A last-in first-out memory having an output connected to the processing unit stores storing the interrupt signals in order of descending priorities. A comparator circuit compares the priority of a new interrupt signal in the storage element with the highest priority interrupt signal currently in the memory. If the new interrupt signal is of the same or a higher priority, an interrupt request signal is sent to the processing unit. Subsequently, the processing unit returns an acknowledge signal which is operative to load the new interrupt signal into the memory, thereby providing the new interrupt signal as an output therefrom. The acknowledge signal also resets the storage element associated with the new interrupt signal.