Patents by Inventor Gerald Peter Beyer

Gerald Peter Beyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11810892
    Abstract: A method of bonding semiconductor components is described. In one aspect a first component, for example a semiconductor die, is bonded to a second component, for example a semiconductor wafer or another die, by direct metal-metal bonds between metal bumps on one component and corresponding bumps or contact pads on the other component. In addition, a number of solder bumps are provided on one of the components, and corresponding contact areas on the other component, and fast solidified solder connections are established between the solder bumps and the corresponding contact areas, without realizing the metal-metal bonds. The latter metal-metal bonds are established in a heating step performed after the soldering step. This enables a fast bonding process applied to multiple dies bonded on different areas of the wafer and/or stacked one on top of the other, followed by a single heating step for realizing metal-metal bonds between the respective dies and the wafer or between multiple stacked dies.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: November 7, 2023
    Assignee: IMEC vzw
    Inventors: Jaber Derakhshandeh, Eric Beyne, Gerald Peter Beyer
  • Publication number: 20210159207
    Abstract: A method of bonding semiconductor components is described. In one aspect a first component, for example a semiconductor die, is bonded to a second component, for example a semiconductor wafer or another die, by direct metal-metal bonds between metal bumps on one component and corresponding bumps or contact pads on the other component. In addition, a number of solder bumps are provided on one of the components, and corresponding contact areas on the other component, and fast solidified solder connections are established between the solder bumps and the corresponding contact areas, without realizing the metal-metal bonds. The latter metal-metal bonds are established in a heating step performed after the soldering step. This enables a fast bonding process applied to multiple dies bonded on different areas of the wafer and/or stacked one on top of the other, followed by a single heating step for realizing metal-metal bonds between the respective dies and the wafer or between multiple stacked dies.
    Type: Application
    Filed: November 23, 2020
    Publication date: May 27, 2021
    Inventors: Jaber Derakhshandeh, Eric Beyne, Gerald Peter Beyer
  • Patent number: 10886252
    Abstract: The disclosed technology generally relates to integrating semiconductor dies and more particularly to bonding semiconductor substrates. In an aspect, a method of bonding semiconductor substrates includes providing a first substrate and a second substrate. Each of the first substrate and the second substrate comprises a dielectric bonding layer comprising one or more a silicon carbon oxide (SiCO) layer, a silicon carbon nitride (SiCN) layer or a silicon carbide (SiC) layer. The method additionally includes, prior to bonding the first and second substrates, pre-treating each of the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate. Pre-treating includes a first plasma activation process in a plasma comprising an inert gas, a second plasma activation process in a plasma comprising oxygen, and a wet surface treatment including a water rinsing step or an exposure to a water-containing ambient.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 5, 2021
    Assignee: IMEC vzw
    Inventors: Lan Peng, Soon-Wook Kim, Eric Beyne, Gerald Peter Beyer, Erik Sleeckx, Robert Miller
  • Patent number: 10141284
    Abstract: The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers. In one aspect, a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometer. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250° C.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: November 27, 2018
    Assignee: IMEC vzw
    Inventors: Soon-Wook Kim, Lan Peng, Patrick Verdonck, Robert Miller, Gerald Peter Beyer, Eric Beyne
  • Publication number: 20180247914
    Abstract: The disclosed technology generally relates to integrating semiconductor dies and more particularly to bonding semiconductor substrates. In an aspect, a method of bonding semiconductor substrates includes providing a first substrate and a second substrate. Each of the first substrate and the second substrate comprises a dielectric bonding layer comprising one or more a silicon carbon oxide (SiCO) layer, a silicon carbon nitride (SiCN) layer or a silicon carbide (SiC) layer. The method additionally includes, prior to bonding the first and second substrates, pre-treating each of the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate. Pre-treating includes a first plasma activation process in a plasma comprising an inert gas, a second plasma activation process in a plasma comprising oxygen, and a wet surface treatment including a water rinsing step or an exposure to a water-containing ambient.
    Type: Application
    Filed: February 28, 2018
    Publication date: August 30, 2018
    Inventors: Lan Peng, Soon-Wook Kim, Eric Beyne, Gerald Peter Beyer, Erik Sleeckx, Robert Miller
  • Publication number: 20170301646
    Abstract: The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers. In one aspect, a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometer. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250° C.
    Type: Application
    Filed: May 24, 2017
    Publication date: October 19, 2017
    Inventors: Soon-Wook Kim, Lan Peng, Patrick Verdonck, Robert Miller, Gerald Peter Beyer, Eric Beyne