Patents by Inventor Gerald R. Friese
Gerald R. Friese has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7843035Abstract: An embodiment of a MIM capacitor includes a first insulating layer formed over a wafer and a first capacitor plate formed over the wafer within the first insulating layer. The MIM capacitor further includes a second insulating layer formed over the first insulating layer, a capacitor dielectric formed over the first capacitor plate within the second insulating layer and a second capacitor plate formed over the capacitor dielectric within the second insulating layer. A recess is formed in the second capacitor plate below an upper surface of the second insulating layer and a catalytic activation layer is formed in the recess.Type: GrantFiled: July 30, 2008Date of Patent: November 30, 2010Assignee: Infineon Technologies AGInventors: Hans-Joachim Barth, Petra Felsner, Erdem Kaltalioglu, Gerald R. Friese
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Publication number: 20080290459Abstract: A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.Type: ApplicationFiled: July 30, 2008Publication date: November 27, 2008Inventors: Hans-Joachim Barth, Petra Felsner, Erdem Kaltalioglu, Gerald R. Friese
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Patent number: 7436016Abstract: A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.Type: GrantFiled: August 23, 2005Date of Patent: October 14, 2008Assignee: Infineon Technologies AGInventors: Hans-Joachim Barth, Petra Felsner, Erdem Kaltalioglu, Gerald R. Friese
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Patent number: 6960835Abstract: In a semiconductor integrated circuit device, thermo-mechanical stresses on the vias can be reduced by introducing a stress relief layer between the vias and a hard dielectric layer that overlies the vias.Type: GrantFiled: October 30, 2003Date of Patent: November 1, 2005Assignees: Infineon Technologies AG, United Microelectronics Co.Inventors: Hans-Joachim Barth, Erdem Kaltalioglu, Mark D. Hoinkis, Gerald R. Friese, Pak Leung
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Patent number: 6949442Abstract: A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.Type: GrantFiled: May 5, 2003Date of Patent: September 27, 2005Assignee: Infineon Technologies AGInventors: Hans-Joachim Barth, Petra Felsner, Erdem Kaltalioglu, Gerald R. Friese
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Patent number: 6872648Abstract: The act of blowing an unpassivated electrical fuse (for example, fuse 405) using a laser can result in the splattering of the fuse material and result in electrical short circuits. A blast barrier (for example blast barrier 406) formed around an area of the fuse that is blown by the laser helps to contain the splattering of the fuse material. The blast barrier may be formed from the same material as the fuses themselves and, therefore, can be created in the same fabrication step.Type: GrantFiled: September 19, 2002Date of Patent: March 29, 2005Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Gerald R. Friese, Andy Cowley, Mohammed Fazil Fayaz, William T. Motsiff
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Publication number: 20040224474Abstract: A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.Type: ApplicationFiled: May 5, 2003Publication date: November 11, 2004Inventors: Hans-Joachim Barth, Petra Felsner, Erdem Kaltalioglu, Gerald R. Friese
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Patent number: 6750113Abstract: A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 &mgr;m) with a bottom etch stop layer, a composite bottom plate having an aluminum layer below a TiN layer, an oxide capacitor dielectric, and a top plate of TiN; in a process that involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.Type: GrantFiled: January 17, 2001Date of Patent: June 15, 2004Assignees: International Business Machines Corporation, Infineon Technologies, AGInventors: Michael D. Armacost, Andreas K. Augustin, Gerald R. Friese, John E. Heidenreich, III, Gary R. Hueckel, Kenneth J. Stein
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Publication number: 20040056322Abstract: The act of blowing an unpassivated electrical fuse (for example, fuse 405) using a laser can result in the splattering of the fuse material and result in electrical short circuits. A blast barrier (for example blast barrier 406) formed around an area of the fuse that is blown by the laser helps to contain the splattering of the fuse material. The blast barrier may be formed from the same material as the fuses themselves and therefore, can be created in the same fabrication step.Type: ApplicationFiled: September 19, 2002Publication date: March 25, 2004Inventors: Gerald R. Friese, Andy Cowley, Mohammed Fazil Fayaz, William T. Motsiff
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Patent number: 6559042Abstract: A process for forming fusible links in an integrated circuit includes forming the fusible link in the last metallization layer. The process can be employed in the fabrication of integrated circuits employing copper metallization and low k dielectric materials. The fusible link is formed in the last metallization layer and may be formed simultaneously with the bonding pad areas.Type: GrantFiled: June 28, 2001Date of Patent: May 6, 2003Assignee: International Business Machines CorporationInventors: Hans-Joachim Barth, Lloyd G. Burrell, Gerald R. Friese, Michael Stetter
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Publication number: 20030003703Abstract: A process for forming fusible links in an integrated circuit includes forming the fusible link in the last metallization layer. The process can be employed in the fabrication of integrated circuits employing copper metallization and low k dielectric materials. The fusible link is formed in the last metallization layer and may be formed simultaneously with the bonding pad areas.Type: ApplicationFiled: June 28, 2001Publication date: January 2, 2003Applicant: International Business Machines CorporationInventors: Hans-Joachim Barth, Lloyd G. Burrell, Gerald R. Friese, Michael Stetter
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Publication number: 20020094656Abstract: A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 &mgr;m) with a bottom etch stop layer, a composite bottom plate having an aluminum layer below a TiN layer, an oxide capacitor dielectric, and a top plate of TiN; in a process that involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.Type: ApplicationFiled: January 17, 2001Publication date: July 18, 2002Applicant: International Business Machines CorporationInventors: Michael D. Armacost, Andreas K. Augustin, Gerald R. Friese, John E. Heidenreich, Gary R. Hueckel, Kenneth J. Stein