Patents by Inventor Gerald R. Talbot

Gerald R. Talbot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230396240
    Abstract: A three-stage differential ring oscillator circuit has a first differential stage, a second differential stage, and a third differential stage and generates six phases (two in each stage) used to form differential in-phase and quadrature-phase clock signals. A cross coupled inverter pair couples the first stage output signals. A second cross coupled inverter pair couples the second stage output signals. A third cross coupled inverter pair couples the third stage output signals. A first interpolator generates a first quadrature-phase clock signal using two phases (one from the positive portion of the second stage and one from the negative portion of the third stage) and a second interpolator generates a second quadrature-phase clock signal using two phases (one from the negative portion of the second stage and one from the positive portion of the third stage). Two phases from the first differential stage form the differential pair of in-phase clock signals.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Inventors: Thomas H. Likens, Gerald R. Talbot
  • Patent number: 11805026
    Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: October 31, 2023
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Stanley Ames Lackey, Jr., Damon Tohidi, Gerald R. Talbot, Edoardo Prete
  • Publication number: 20230342325
    Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a non-PCIe protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a non-PCIe format, encapsulating the non-PCIe format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.
    Type: Application
    Filed: June 30, 2023
    Publication date: October 26, 2023
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Gordon Caruk, Maurice B. Steinman, Gerald R. Talbot, Joseph D. Macri
  • Publication number: 20230308132
    Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. In order to better handle noise issues when using single-ended signaling, one or more of the receivers include equalization circuitry and termination circuitry. The termination circuitry prevents reflection on a corresponding transmission line ending at a corresponding receiver. The equalization circuitry uses a bridged T-coil circuit to provide continuous time linear equalization (CTLE) with no feedback loop. The equalization circuitry performs equalization by providing a high-pass filter that offsets the low-pass characteristics of a corresponding transmission line. A comparator of the receiver receives the input signal and compares it to a reference voltage.
    Type: Application
    Filed: March 25, 2022
    Publication date: September 28, 2023
    Inventors: Dean E. Gonzales, Edoardo Prete, Milam Paraschou, Mark Chirachanchai, Gerald R. Talbot
  • Publication number: 20230305979
    Abstract: Systems, apparatuses, and methods for implementing a periodic receiver clock data recovery scheme with dynamic data edge paths are disclosed. An IQ link calibration scheme performs a non-destructive data and edge path switch to determine an IQ offset without disturbing the data. A data path and an edge path pass through multiple stages of deserializers to widen the data path, with the deserializers clocked by clock divided versions of the original data and edge clocks. To initiate a calibration routine, the edge clock is aligned with the data clock, and then data and edge paths are swapped at a common point in a slower clock domain. The data path is then calibrated while the edge path carries the data signal. After the data path is calibrated, the edge and data paths are swapped back to the original configuration.
    Type: Application
    Filed: March 25, 2022
    Publication date: September 28, 2023
    Inventors: Gurunath Dollin, Edoardo Prete, Milam Paraschou, Edward Wade Thoenes, Ryan J. Hensley, Gerald R. Talbot
  • Patent number: 11693813
    Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a Gen-Z protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a Gen-Z format, encapsulating the Gen-Z format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: July 4, 2023
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Gordon Caruk, Maurice B. Steinman, Gerald R. Talbot, Joseph D. Macri
  • Publication number: 20230195678
    Abstract: A semiconductor package for skew matching in a die-to-die interface, including: a first die; a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die; and a plurality of connection paths of a substantially same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.
    Type: Application
    Filed: March 10, 2022
    Publication date: June 22, 2023
    Inventors: PRADEEP JAYARAMAN, DEAN GONZALES, GERALD R. TALBOT, RAMON A. MANGASER, MICHAEL J. TRESIDDER, PRASANT KUMAR VALLUR, SRIKANTH REDDY GRUDDANTI, KRISHNA REDDY MUDIMELA VENKATA, DAVID H. MCINTYRE
  • Publication number: 20230134926
    Abstract: Systems, apparatuses, and methods for implementing a combo scheme for direct current (DC) level shifting of signals are disclosed. A receiver circuit receives an input signal on a first interface. The first interface is coupled to a resistor in parallel with a capacitor which passes the input signal to a second interface. Also, the first interface is coupled to a first pair of current sources between ground and a voltage source, and the second interface is coupled to a second pair of current sources between ground and the voltage source. An op-amp drives the current sources based on a difference between a sensed common mode voltage and a reference voltage. Based on this circuit configuration, the receiver circuit is able to prevent baseline wander, perform a DC level shift of the input signal, and achieve linear equalization of the input signal.
    Type: Application
    Filed: December 30, 2021
    Publication date: May 4, 2023
    Inventors: Rajesh Kumar, Edoardo Prete, Gerald R. Talbot, Ethan Crain, Tracy J. Feist, Jeffrey Cooper
  • Patent number: 11283589
    Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: March 22, 2022
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Varun Gupta, Milam Paraschou, Gerald R. Talbot, Gurunath Dollin, Damon Tohidi, Eric Ian Carpenter, Chad S. Gallun, Jeffrey Cooper, Hanwoo Cho, Thomas H. Likens, III, Scott F. Dow, Michael J. Tresidder
  • Publication number: 20220035765
    Abstract: An interconnect controller for a data processing platform includes a data link layer controller for selectively receiving data packets from and sending data packets to a higher protocol layer, and a physical layer controller coupled to the data link layer controller and adapted to be coupled to a communication link. The physical layer controller operates according to a predetermined protocol selectively at one of a plurality of enhanced speeds that are not specified by any published standard and are separated from each other by the same predetermined amount. In response to performing a link initialization, the interconnect controller performs at least one setup operation to select a speed, and subsequently operates the communication link using a selected speed.
    Type: Application
    Filed: October 18, 2021
    Publication date: February 3, 2022
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Gordon Caruk, Gerald R. Talbot
  • Patent number: 11151075
    Abstract: An interconnect controller includes a data link layer controller coupled to a transaction layer, wherein the data link layer controller selectively receives data packets from and sends data packets to the transaction layer, and a physical layer controller coupled to the data link layer controller and to a communication link. The physical layer controller selectively operates at a first predetermined link speed. The physical layer controller has an enhanced speed mode, wherein in response to performing a link initialization, the interconnect controller queries a data processing platform to determine whether the enhanced speed mode is permitted, performs at least one setup operation to select an enhanced speed, wherein the enhanced speed is greater than the first predetermined link speed, and subsequently operates the communication link using the enhanced speed.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: October 19, 2021
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Gordon Caruk, Gerald R. Talbot
  • Publication number: 20210111861
    Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Inventors: Varun Gupta, Milam Paraschou, Gerald R. Talbot, Gurunath Dollin, Damon Tohidi, Eric Ian Carpenter, Chad S. Gallun, Jeffrey Cooper, Hanwoo Cho, Thomas H. Likens, III, Scott F. Dow, Michael J. Tresidder
  • Publication number: 20210028995
    Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.
    Type: Application
    Filed: August 14, 2020
    Publication date: January 28, 2021
    Inventors: Stanley Ames Lackey, JR., Damon Tohidi, Gerald R. Talbot, Edoardo Prete
  • Patent number: 10873445
    Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: December 22, 2020
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Varun Gupta, Milam Paraschou, Gerald R. Talbot, Gurunath Dollin, Damon Tohidi, Eric Ian Carpenter, Chad S. Gallun, Jeffrey Cooper, Hanwoo Cho, Thomas H. Likens, III, Scott F. Dow, Michael J. Tresidder
  • Publication number: 20200344039
    Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.
    Type: Application
    Filed: December 10, 2019
    Publication date: October 29, 2020
    Inventors: Varun Gupta, Milam Paraschou, Gerald R. Talbot, Gurunath Dollin, Damon Tohidi, Eric Ian Carpenter, Chad S. Gallun, Jeffrey Cooper, Hanwoo Cho, Thomas H. Likens, III, Scott F. Dow, Michael J. Tresidder
  • Patent number: 10749756
    Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: August 18, 2020
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Stanley Ames Lackey, Jr., Damon Tohidi, Gerald R. Talbot, Edoardo Prete
  • Patent number: 10749552
    Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: August 18, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Balwinder Singh, Milam Paraschou, Chad S. Gallun, Jeffrey Cooper, Dean E. Gonzales, Alushulla Jack Ambundo, Thomas H. Likens, III, Gerald R. Talbot
  • Patent number: 10698856
    Abstract: A link controller, method, and data processing platform are provided with dual-protocol capability. The link controller includes a physical layer circuit for providing a data lane over a communication link, a first data link layer controller which operates according to a first protocol, and a second data link layer controller which operates according to a second protocol. A multiplexer/demultiplexer selectively connects both data link layer controllers to the physical layer circuit. A link training and status state machine (LTSSM) selectively controls the physical layer circuit to transmit and receive first training ordered sets over the data lane, and inside the training ordered sets, transmit and receive alternative protocol negotiation information over the data lane. In response to receiving the alternative protocol negotiation information, the LTSSM causes the multiplexer/demultiplexer to selectively connect the physical layer circuit to the second data link layer controller.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: June 30, 2020
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Gordon Caruk, Gerald R. Talbot
  • Patent number: 10692545
    Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: June 23, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Milam Paraschou, Balwinder Singh, Gerald R. Talbot, Alushulla Jack Ambundo, Edoardo Prete, Thomas H. Likens, III, Michael A. Margules
  • Publication number: 20200192853
    Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a Gen-Z protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a Gen-Z format, encapsulating the Gen-Z format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.
    Type: Application
    Filed: May 30, 2019
    Publication date: June 18, 2020
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Gordon Caruk, Maurice B. Steinman, Gerald R. Talbot, Joseph D. Macri