Abstract: A phase selection circuit having a selection circuit, binary weighted current sources, and an amplifier circuit. The phase selection circuit is configured for selecting adjacent phase signals from a number of equally-spaced phases of a clock signal, based on a phase selection value. The selection circuit outputs the adjacent phase signals to respective first and second binary weighted current sources, along with a digital interpolation value. The first current source outputs a contribution current onto a summing node based on the first adjacent phase signal and the digital interpolation control value, and the second current source outputs a second contribution current to the summing node based on the second adjacent phase signal and an inverse of the digital interpolation control value, resulting in an interpolated signal. An amplifier circuit outputs the interpolated signal as a phase-interpolated clock signal according to the phase selection value.

Abstract: A method of ensuring robust operation of a differential serial link is provided. The method provides a first integrated circuit having 1) a phase generator constructed and arranged to provide a programmable shift of a clock signal based on selective interpolating between first and second phases of the clock signal relative to a digital phase value, and 2) a transmit driver constructed and arranged to control, in a programmable manner, a differential voltage of digital data signals. A second integrated circuit is constructed and arranged to receive the clock and digital data signals sent by the first integrated circuit. The clock and digital data signals are sent substantially simultaneously through the link from the first integrated circuit to the second integrated circuit. It is determined whether the digital data signals can be sampled reliably by the second integrated circuit relative to the digital phase value.

Abstract: A serial link system is provided for determining a worst-case cumulative data eye. The system includes a transmitter, a receiver, and a channel between the transmitter and receiver such that data sent by the transmitter is received by the receiver through the channel. The channel includes a plurality of connections including a victim and at least first and second aggressors, with the victim being disposed between the first and second aggressors. The system also includes a controller constructed and arranged to determine a worst case cumulative data eye based on a data pattern of the victim, jitter on the victim, an effect a data and jitter pattern on the first aggressor has on the victim and an effect a data and jitter pattern of the second aggressor has on the victim and to combine the effects of the data pattern of the victim, the jitter on the victim and the effects of the first and second aggressors on the victim into a single pattern to determine cumulative data eye for use in a simulator.

Abstract: An integrated device (e.g., an integrated PCI bridge device) buffers received PCI bus strobe signals and distributes strobe signals for PCI receive data relative to the PCI data lines, enabling all PCI receive data to be latched using locally-generated PCI strobe signals generated based on the same PCI bus strobe signals. In addition, data line latch modules having primary and secondary flip-flops enable the PCI receive data to be held for an entire clock cycle, optimizing conversion between a PCI clock domain and a local clock domain of the PCI bridge device. A transmission circuit also can be configured to transmit data according to either double data rate (DDR) mode or quad data rate (QDR) mode in an efficient manner.

Abstract: A phase alignment circuit having a phase selection circuit, a synchronizer, and a counter form a feedback loop for aligning a local clock signal with a received reference clock of a synchronous communications system. The phase selection circuit is configured for outputting the local clock signal as a phase-adjusted local clock having a selected phase based on a phase selection value specified by the counter. The synchronizer is configured for digitally sampling the received reference clock relative to the phase-adjusted local clock, and outputting a digital phase bit identifying whether the phase-adjusted local clock has a later phase relative to the received reference clock. The counter selectively increments or decrements a counted value based on the digital phase bit, and outputs to the phase selection circuit a prescribed number of most significant bits from the counted value as the phase selection value.

Abstract: An even number phase ring oscillator having at least eight, equally spaced phases. The oscillator includes at least eight stages, defining at least four pairs of stages, with each pair including a first stage and an associated second stage. The first stages are arranged such that an output of a first stage defines a primary input of another first stage, with the output of the first stage of the last pair defining the primary input of the second stage of the first pair. The second stages are arranged such that an output of a second stage defines a primary input of an another second stage, with the output of the second stage of the last pair crossing over the output of the first stage of the last pair and defining a primary input of the first stage of the first pair, thereby defining a closed loop.

Abstract: Access is provided to internal analog voltage signals on internal analog nodes of an integrated circuit, without distortion of the internal analog voltage signals. An integrated circuit includes a voltage access circuit having buffered multiplexer circuits in proximity to respective groups of internal analog nodes for respective internal analog voltage signals. Each voltage access circuit outputs a selected one of the corresponding group of internal analog voltage signals as a buffered analog node signal. The voltage access circuit also includes a buffering output circuit configured for outputting a selected one of the buffered analog node signals from the respective buffered multiplexer circuits, as a buffered voltage signal, to an output pad configured for supplying the buffered voltage signal to an external probe. Successively larger buffer stages minimize loading on the internal analog nodes, while providing sufficient power for outputting the buffered voltage signal to the external probe.

Abstract: An integrated circuit includes a dual mode output driver configured for outputting an output signal according to either a high voltage mode or a low voltage mode, and a controller for controlling the dual mode output driver at the selected mode. The dual mode output driver includes a high-voltage pull-up/pull-down driver circuit and a low-voltage pull-up/pull-down driver circuit, the low-voltage pull-down transistor in series with the high-voltage pull-down transistor that is coupled to the output node. Protection circuitry prevents the low-voltage transistors from encountering an overvoltage condition during the high voltage mode, and controls the slew rate of the output signal during the low voltage mode.

Abstract: An integrated device includes a voltage mode transmit driver for matching an output impedance to an output transmission line based on a binary code, an input termination module configured for matching an input impedance to an input transmission line based on an input impedance calibration value using thermometer-based decoding. The voltage mode transmit driver includes, for each differential output signal, a resistor network circuit having pull-up circuits and pull-down circuits for changing the voltage on the differential output signal, and having binary weighted resistance values relative to each other. The input termination module includes pull-up circuits and pull-down circuits having inverse hyperbolic resistance values relative to each other, and using thermometer-based decoding to ensure a linear change in input impedance during transitions in the input impedance calibration value.