Abstract: Technologies for application-specific network acceleration include a computing device including a processor and an accelerator device such as a field-programmable gate array (FPGA). The processor and the accelerator device are coupled via a coherent interconnect and may be included in a multi-chip package. The computing device binds a virtual machine executed by the processor with an application function unit of the accelerator device via the coherent interconnect. The computing device processes network application data with the virtual machine and the application function unit within a coherency domain maintained with the coherent interconnect. Processing the network data may include processing a packet of a network flow by the virtual machine and processing subsequent packets of the network flow by the application function unit. Other embodiments are described and claimed.

Abstract: A computer system may comprise a multi-chip package (MCP), which includes multi-core processor circuitry and hardware accelerator circuitry. The multi-core processor circuitry may comprise a plurality of processing cores, and the hardware accelerator circuitry may be coupled with the multi-core processor circuitry via one or more coherent interconnects and one or more non-coherent interconnects. A coherency domain of the MCP may be extended to encompass the hardware accelerator circuitry, or portions thereof An interconnect selection module may select an individual coherent interconnect or an individual non-coherent interconnect based on application requirements of an application to be executed and a workload characteristic policy. Other embodiments are described and/or claimed.

Abstract: Technologies for application-specific network acceleration include a computing device including a processor and an accelerator device such as a field-programmable gate array (FPGA). The processor and the accelerator device are coupled via a coherent interconnect and may be included in a multi-chip package. The computing device binds a virtual machine executed by the processor with an application function unit of the accelerator device via the coherent interconnect. The computing device processes network application data with the virtual machine and the application function unit within a coherency domain maintained with the coherent interconnect. Processing the network data may include processing a packet of a network flow by the virtual machine and processing subsequent packets of the network flow by the application function unit. Other embodiments are described and claimed.

Abstract: A disposable moisture detection component manufactured from a water soluble conductive polymer film-forming and printable mixture with a resistivity of 100 ohms or less. Moisture detection component is embedded in incontinent articles such as diapers and bedpans. Conductive polymer dissolves in the presences of urine or feces and when connected to an electronic circuit, provides diaper status to a caregiver.

Abstract: Wireless moisture detection system using water soluble insulated wire or water soluble conductors as sensor inputs to a programmed microcontroller to determine if the water soluble sensors have been penetrated by moisture dissolving the soluble materials and changing the electrical characteristics of the sensor providing an interrupt to the microcontroller to signal the presence of moisture for the monitor to wirelessly communicate to the monitoring system.

Abstract: Wireless moisture detection system using water soluble insulated wire or water soluble conductors as sensor inputs to a programmed microcontroller to determine if the water soluble sensors have been penetrated by moisture dissolving the soluble materials and changing the electrical characteristics of the sensor providing an interrupt to the microcontroller to signal the presence of moisture for the monitor to wirelessly communicate to the monitoring system.

Abstract: Wireless moisture detection system using water soluble insulated wire or water soluble conductors as sensor inputs to a programmed microcontroller to determine if the water soluble sensors have been penetrated by moisture dissolving the soluble materials and changing the electrical characteristics of the sensor providing an interrupt to the microcontroller to signal the presence of moisture for the monitor to wirelessly communicate to the monitoring system.

Abstract: Wireless moisture detection system using water soluble insulated wire or water soluble conductors as sensor inputs to a programmed microcontroller to determine if the water soluble sensors have been penetrated by moisture dissolving the soluble materials and changing the electrical characteristics of the sensor providing an interrupt to the microcontroller to signal the presence of moisture for the monitor to wirelessly communicate to the monitoring system.

Abstract: Technologies for application-specific network acceleration include a computing device including a processor and an accelerator device such as a field-programmable gate array (FPGA). The processor and the accelerator device are coupled via a coherent interconnect and may be included in a multi-chip package. The computing device binds a virtual machine executed by the processor with an application function unit of the accelerator device via the coherent interconnect. The computing device processes network application data with the virtual machine and the application function unit within a coherency domain maintained with the coherent interconnect. Processing the network data may include processing a packet of a network flow by the virtual machine and processing subsequent packets of the network flow by the application function unit. Other embodiments are described and claimed.

Abstract: A computer system may comprise a multi-chip package (MCP), which includes multi-core processor circuitry and hardware accelerator circuitry. The multi-core processor circuitry may comprise a plurality of processing cores, and the hardware accelerator circuitry may be coupled with the multi-core processor circuitry via one or more coherent interconnects and one or more non-coherent interconnects. A coherency domain of the MCP may be extended to encompass the hardware accelerator circuitry, or portions thereof An interconnect selection module may select an individual coherent interconnect or an individual non-coherent interconnect based on application requirements of an application to be executed and a workload characteristic policy. Other embodiments are described and/or claimed.

Abstract: A vibration sensor device can be used with smartphones, tablets and computers with application software for measuring vibration frequency, damping coefficient and scale factor isolating the measurement to the specific area of the vibration sensor clamped to the vibrating system. Vibration sensor powered by the microphone bias found with CTIA and OMTP compatible systems and does not require batteries or external power.

Abstract: A computerized system, method and device for assisting in the tuning of a musical instrument to a user identified reference pitch comprising, a vibration sensor attachable to a musical instrument wirelessly connected to a computer device such as an iPhone, Android tablet, Windows phone, or other such smart devices (SD) having a display screen and software for receiving vibration data and computing and displaying the difference between the user input pitch and the instrument vibration frequency computed from the vibration data as, sharp, flat, or in tune, to tune the instrument. The system further provides a choice of either an audio or vibration alert signals for directing the user to increase or decrease the tone of the musical instrument matching the reference pitch enabling even visually impaired musicians who may not be able to visualize the data on a touch screen display of the smart device, to tune their instruments.

Abstract: A computerized system and method for music practice and training to assist a musician to improve their skills in maintaining a tempo and to improve ear-hand coordination, eye-hand coordination and other motor skills while learning to play an instrument. The system receives user defined beats per minute (BPM), rhythms or short segments of a music piece and generates audio reference outputs and visual display of music notes as stimuli. The user responses to these stimuli are measured in time and in the force and intensity of the responses and provided as feedback to the user to improve their response time and intensity to stimuli and assists the user in modifying the responses to the output stimuli to reduce the time between the output stimuli and the user response and thus improve the user's timing accuracy while playing music.

Abstract: A computerized system and method for music practice and training to assist a musician to improve their skills in maintaining a tempo and to improve ear-hand coordination, eye-hand coordination and other motor skills while learning to play an instrument. The system receives user defined beats per minute (BPM), rhythms or short segments of a music piece and generates audio reference outputs and visual display of music notes as stimuli. The user responses to these stimuli are measured in time and in the force and intensity of the responses and provided as feedback to the user to improve their response time and intensity to stimuli and assists the user in modifying the responses to the output stimuli to reduce the time between the output stimuli and the user response and thus improve the user's timing accuracy while playing music.

Abstract: Apparatuses, methods and storage media associated with integrated circuits (IC) or system-on-chips (SOC) are disclosed herein. In embodiments, a multi-core IC may include a number of central processing units (CPUs), and a number of input/output (I/O) resources. The IC may further include a switch fabric configured to couple the CPUs with the I/O resources, and a register to be selectively configured to exclusively couple one of the CPUs with one of the I/O resources to form a logical domain that computationally isolates the one CPU and the one I/O resource from other CPUs and other I/O. Other embodiments may be described and claimed.

Abstract: Apparatuses, methods and storage media associated with integrated circuits (IC) or system-on-chips (SOC) are disclosed herein. In embodiments, a multi-core IC may include a number of central processing units (CPUs), and a number of input/output (I/O) resources. The IC may further include a switch fabric configured to couple the CPUs with the I/O resources, and a register to be selectively configured to exclusively couple one of the CPUs with one of the I/O resources to form a logical domain that computationally isolates the one CPU and the one I/O resource from other CPUs and other I/O. Other embodiments may be described and claimed.

Abstract: A two player game apparatus includes the inputs for the first and second player, together with display for each player with a common display for providing the game status connected to a single electronic digital processor. The processor system further includes two central processing units where one central processing unit performs the game algorithm for one player and the second central processing unit performs the game algorithm for the second player. Each individual's central processing unit provides individual player status for its player input. Both central processing units provide data for the common display.

Abstract: An electronic digital processing system implemented on a single MOS/LSI semiconductor chip including a ROM for storing instruction codes, a RAM for storing data, an arithmetic logic unit for performing operations on data under control of microinstructions or commands, control circuitry for generating commands in response to the instruction codes in a plurality of central processing units. The fetching of instructions from the ROM, the accessing of data from the RAM, the operation of the arithmetic unit are controlled by the central processing units which share the same data paths that couple the central processing units to the ROM, RAM, arithmetic unit and control circuitry.

Abstract: An electronic apparatus with processing capability dedicated to the display function. This apparatus includes a keyboard for inputting data into the processor system and a display for presentation of the output data from the processor system. The electronic digital processor system includes a memory, an arithmetic and logic unit and two central processing units that operate independently and simultaneously. The keyboard input is connected to one central processing unit and the display is connected to the second central processing unit. The algorithm in the first central processing unit is dedicated to obtaining inputs from the keyboard and performing certain operations defined by the function of the apparatus. The algorithm contained in the second central processing unit is dedicated to the display of output data contained in a RAM in the digital processor system. Since both central processing units operate simultaneously and independently, they both use the same locations in RAM.

Abstract: An electronic digital processor system including a plurality of processing units with dedicated input port and output port for each of the processing units and an output port that is shared by the processing units. The digital processor system also includes a ROM for the storage of commands, a RAM for the storage of data, an arithmetic and logic unit for performing operations on the data, two independent and simultaneously operable processing units for executing these commands on the data and the control circuit for providing for simultaneous execution of commands in both processing units.