Patents by Inventor Gerald S Chan

Gerald S Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process for improving design-limited yield by localizing potential faults from production test data
    Patent number: 8615691
    Abstract: A process for improving design-limited yield by collecting test fail data, converting to electrical faults, and localizing to physical area on semiconductor die. The steps of identifying an area on a wafer containing a fault to enable the analysis of specific defects, accumulating data suitable for yield monitoring analysis based on pattern test failures logged on scan cells in scan chains on automatic test equipment, and translating scan cell and scan chain failure reports to geometric locations of electrical structures on wafers.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: December 24, 2013
    Assignee: Advantest (Singapore) Pte Ltd
    Inventors: Richard C Dokken, Gerald S. Chan, John C Potter, Alfred L Crouch
  • Process for improving design limited yield by efficiently capturing and storing production test data for analysis using checksums, hash values, or digital fault signatures
    Patent number: 8453026
    Abstract: A process for conserving storage space and time while recording not only a pass or fail result per die but also additional failure test pattern data by computing and comparing digital fault signatures or hash values on a tester.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: May 28, 2013
    Assignee: Advantest (Singapore) Pte Ltd
    Inventors: Gerald S. Chan, Richard C. Dokken
  • Method for operating a secure semiconductor IP server to support failure analysis
    Patent number: 8060851
    Abstract: A method for operating a secure semiconductor IP access server to support failure analysis. A client presents a test failure and failure type to an automated server which traverses an electronic product design, definition, and test database to report specifically those components and interconnect likely to cause the failure with geometrical information which may be displayed on the client. Other aspects of semiconductor IP are protected by the server by limiting the trace mechanism and renaming components.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: November 15, 2011
    Assignee: Verigy (Singapore) Pte. Ltd.
    Inventors: Richard C. Dokken, Gerald S. Chan, Jacob J Orbon, Alfred L Crouch
  • System and method for device performance characterization in physical and logical domains with AC SCAN testing
    Patent number: 8006149
    Abstract: A method for data logging from inside a semiconductor device, yielding timing performance information about the logic behind each and every flip-flop in the scan chain and displaying the sensitivity of certain flipflops to speed related manufacturing defects. The method comprises steps for testing, measuring, storing, and analyzing records for frequency characterization of complex digital semiconductors.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: August 23, 2011
    Assignee: Verigy (Singapore) Pte. Ltd.
    Inventors: Richard C. Dokken, Gerald S. Chan, Phillip D. Burlison
  • METHOD FOR OPERATING A SECURE SEMICONDUCTOR IP SERVER TO SUPPORT FAILURE ANALYSIS
    Publication number: 20100031092
    Abstract: A method for operating a secure semiconductor IP access server to support failure analysis. A client presents a test failure and failure type to an automated server which traverses an electronic product design, definition, and test database to report specifically those components and interconnect likely to cause the failure with geometrical information which may be displayed on the client. Other aspects of semiconductor IP are protected by the server by limiting the trace mechanism and renaming components.
    Type: Application
    Filed: September 5, 2007
    Publication date: February 4, 2010
    Applicant: INOVYS CORPORATION
    Inventors: RICHARD C. DOKKEN, GERALD S. CHAN, JACOB J. ORBON, ALFRED L. CROUCH
  • Process for identifying the location of a break in a scan chain in real time
    Patent number: 7568139
    Abstract: A process for identifying the location of a break in a scan chain in real time as fail data is collected from a tester. Processing a test pattern before applying it on a tester provides a signature enabling a method for a tester to identify a scan cell which is stuck during the time the tester is operating on a device under test rather than accumulating voluminous test data sets for delayed offline analysis.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: July 28, 2009
    Assignee: Inovys Corporation
    Inventors: Richard C Dokken, Gerald S Chan, Takehiko Ishii
  • PROCESS FOR IDENTIFYING THE LOCATION OF A BREAK IN A SCAN CHAIN IN REAL TIME
    Publication number: 20080141085
    Abstract: A process for identifying the location of a break in a scan chain in real time as fail data is collected from a tester. Processing a test pattern before applying it on a tester provides a signature enabling a method for a tester to identify a scan cell which is stuck during the time the tester is operating on a device under test rather than accumulating voluminous test data sets for delayed offline analysis.
    Type: Application
    Filed: December 12, 2006
    Publication date: June 12, 2008
    Applicant: INOVYS CORPORATION
    Inventors: Richard C. Dokken, Gerald S. Chan, Takehiko Ishii
  • System and Method for Device Performance Characterization in Physical and Logical Domains with AC SCAN Testing
    Publication number: 20080126896
    Abstract: A method for data logging from inside a semiconductor device, yielding timing performance information about the logic behind each and every flip-flop in the scan chain and displaying the sensitivity of certain flipflops to speed related manufacturing defects. The method comprises steps for testing, measuring, storing, and analyzing records for frequency characterization of complex digital semiconductors.
    Type: Application
    Filed: November 27, 2006
    Publication date: May 29, 2008
    Applicant: INOVYS CORPORATION
    Inventors: Richard C. Dokken, Gerald S. Chan, Phillip D. Burlison
  • Process for improving design limited yield by efficiently capturing and storing production test data for analysis using checksums, hash values, or digital fault signatures
    Publication number: 20080104468
    Abstract: A process for conserving storage space and time while recording not only a pass or fail result per die but also additional failure test pattern data by computing and comparing digital fault signatures or hash values on a tester.
    Type: Application
    Filed: November 30, 2006
    Publication date: May 1, 2008
    Applicant: INOVYS CORPORATION
    Inventors: GERALD S. CHAN, RICHARD C. DOKKEN
  • PROCESS FOR IMPROVING DESIGN-LIMITED YIELD BY LOCALIZING POTENTIAL FAULTS FROM PRODUCTION TEST DATA
    Publication number: 20080091981
    Abstract: A process for improving design-limited yield by collecting test fail data, converting to electrical faults, and localizing to physical area on semiconductor die. The steps of identifying an area on a wafer containing a fault to enable the analysis of specific defects, accumulating data suitable for yield monitoring analysis based on pattern test failures logged on scan cells in scan chains on automatic test equipment, and translating scan cell and scan chain failure reports to geometric locations of electrical structures on wafers.
    Type: Application
    Filed: March 6, 2007
    Publication date: April 17, 2008
    Applicant: INOVYS CORPORATION
    Inventors: RICHARD C. DOKKEN, Gerald S. Chan, John C. Potter, Alfred L. Crouch