Patents by Inventor Gerald S. Stellenberg

Gerald S. Stellenberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8259715
    Abstract: A method for load balancing selects one of a set of distribution formulas to associate packets of each of multiple communications sessions traversing a link to one of a plurality of output links and assigns the associated packets of at least one of the communications sessions to a different output link.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: September 4, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Gerald S. Stellenberg, Brian C. Smith, James M. Rolette
  • Publication number: 20090028045
    Abstract: A method for load balancing selects one of a set of distribution formulas to associate packets of each of multiple communications sessions traversing a link to one of a plurality of output links and assigns the associated packets of at least one of the communications sessions to a different output link.
    Type: Application
    Filed: July 25, 2007
    Publication date: January 29, 2009
    Applicant: 3Com Corporation
    Inventors: Gerald S. Stellenberg, Brian C. Smith, James M. Rolette
  • Publication number: 20080279189
    Abstract: A method and system for introducing controlled delay of packet processing at a network entity using multiple delay loop paths (DLPs). For each packet received at the network entity, a determination will be made as to whether or not processing should be delayed. If delay is necessary, one of a plurality of DLPs will be selected according to a desired delay for the packet and a path delay determined for each DLP. Upon completion of a DLP delay, a packet will be returned for processing, an additional delay, or some other action. Multiple DLPs may be enabled with packet queues, and may be used advantageously by security devices, such as Intrusion Prevention Systems (and other packet processing platforms) for which in-order processing of packets may be desired or required.
    Type: Application
    Filed: May 7, 2007
    Publication date: November 13, 2008
    Applicant: 3COM CORPORATION
    Inventors: Brian C. Smith, Gerald S. Stellenberg
  • Patent number: 7134143
    Abstract: A pattern matching engine supports high speed (up to at least 2.4. Gbits per second line rate speeds) parallel pattern matching operations in an unanchored fashion. The engine is preferably implemented as a hardware device. A shift register serially receives a string of data stream bytes which are partitioned into a plurality of multi-byte overlapping adjacent stream chunks. Library patterns of bytes to be searched for are similarly partitioned into multi-byte overlapping adjacent table chunks for storage in a look-up table. The plurality of multi-byte overlapping adjacent stream chunks are applied by the register in parallel to the look-up table, with a result being returned which is indicative of whether each stream chunk matches one of the look-up table stored table chunks. The results of the parallel look-up operation are then logically combined to make a match determination.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: November 7, 2006
    Inventors: Gerald S. Stellenberg, Joaquin J. Aviles
  • Patent number: 6914901
    Abstract: A method for communicating data is provided that includes communicating a first set of data from a first channel to a first serial-to-parallel converter and communicating a second set of data from a second channel to a second serial-to-parallel converter, the data sets are then converted to a parallel format. The converters are monitored to determine when one or more words of the respective data sets have accumulated in each of the converters. One or more of the words that have accumulated in each of the converters are then written to a selected one of first and second memory banks. A single scheduler monitors the memory banks to determine when the words that were written to each of the memory banks have formed one or more cells such that they may be read out of a selected one of the memory banks to be communicated to an output communications link.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: July 5, 2005
    Assignee: Cisco Technology, Inc.
    Inventors: William P. Hann, Gerald S. Stellenberg
  • Publication number: 20040151382
    Abstract: A pattern matching engine supports high speed (up to at least 2.4. Gbits per second line rate speeds) parallel pattern matching operations in an unanchored fashion. The engine is preferably implemented as a hardware device. A shift register serially receives a string of data stream bytes which are partitioned into a plurality of multi-byte overlapping adjacent stream chunks. Library patterns of bytes to be searched for are similarly partitioned into multi-byte overlapping adjacent table chunks for storage in a look-up table. The plurality of multi-byte overlapping adjacent stream chunks are applied by the register in parallel to the look-up table, with a result being returned which is indicative of whether each stream chunk matches one of the look-up table stored table chunks. The results of the parallel look-up operation are then logically combined to make a match determination.
    Type: Application
    Filed: February 4, 2003
    Publication date: August 5, 2004
    Applicant: TippingPoint Technologies, Inc.
    Inventors: Gerald S. Stellenberg, Joaquin J. Aviles