Patents by Inventor Gerald Shipley

Gerald Shipley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Test vehicle data analysis
    Patent number: 7370257
    Abstract: A system and method for collecting and analyzing integrated circuit test vehicle test data by identifying various blocks of circuitry through at least two different intersecting test paths. In one embodiment, the process test circuits may be arranged in a matrix format and connected so that they may be tested along rows or columns. When a failure along a specific row and a specific column is identified, the process test circuit at the intersection may be identified as the failure point.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: May 6, 2008
    Assignee: LSI Logic Corporation
    Inventors: Richard Schultz, Gerald Shipley, Derryl Allman
  • Process for identifying duplicate values in very large data sets
    Publication number: 20070071240
    Abstract: The present invention is directed to a method of identifying duplicate data elements in large data sets. This involves receiving the data sets. Dividing each data element in the data set into a series of data segments to define data keys. Generating an intermediate value for the each element in the data set using summed values for the data keys. Sorting the data entries using the intermediate values. Sorting the matched intermediate value entries using the data keys. Identifying the duplicate data elements in the data set.
    Type: Application
    Filed: September 12, 2005
    Publication date: March 29, 2007
    Inventors: Gerald Shipley, David Castaneda
  • Test vehicle data analysis
    Publication number: 20060242522
    Abstract: A system and method for collecting and analyzing integrated circuit test vehicle test data by identifying various blocks of circuitry through at least two different intersecting test paths. In one embodiment, the process test circuits may be arranged in a matrix format and connected so that they may be tested along rows or columns. When a failure along a specific row and a specific column is identified, the process test circuit at the intersection may be identified as the failure point.
    Type: Application
    Filed: April 8, 2005
    Publication date: October 26, 2006
    Applicant: LSI Logic Corporation
    Inventors: Richard Schultz, Gerald Shipley, Derryl Allman