Abstract: A rate generator for generating a plurality of different frequencies that represent video requests in a video on demand (VOD) system. The rate generator comprises a plurality of parallel groups, each group comprising a phase accumulator module having a plurality of phase accumulators, a phase increment model having a plurality of phase increment registers, and an adder, coupled to the phase accumulator module and the phase increment module. The adder sums the phase increment value from the phase from the phase increment module and the output of the phase accumulator module and provides the value back to the phase accumulator module. When the sum reaches a pre-determined value, the adder resets and generates a pulse at a frequency dependent on the phase increment and the sampling frequency. In addition, a method for deriving the rate generator architecture is also provided.

Abstract: A rate generator for generating a plurality of different frequencies that represent video requests in a video on demand (VOD) system. The rate generator comprises a plurality of parallel groups, each group comprising a phase accumulator module having a plurality of phase accumulators, a phase increment model having a plurality of phase increment registers, and an adder, coupled to the phase accumulator module and the phase increment module. The adder sums the phase increment value from the phase from the phase increment module and the output of the phase accumulator module and provides the value back to the phase accumulator module. When the sum reaches a pre-determined value, the adder resets and generates a pulse at a frequency dependent on the phase increment and the sampling frequency. In addition, a method for deriving the rate generator architecture is also provided.

Abstract: A hierarchical stack filter performs nonlinear filtering operations such as median filtering and other rank-order filtering. The stack filter has a number of stages in the stack which equals the number of bits in the words of the input word sequence, and each filter of the stack receives as a first input signal a window of the input sequence. Each filter stage has an expansion input port and an expansion output port. Each filter stage calculates a residue and couples the residue from its expansion output port to expansion input port of the filter stage of next lesser significance.

Abstract: A display processor, as for a small computer, processes pixel codes of various lengths. Three addressable color maps have their read addresses generated independently from portions of each pixel code. The portions of each pixel code used in generating each read address can be selected by programming.

Abstract: A bistable solid-state device, substantially immune to long term, low level radiation comprises, in combination with memory storage elements, means comprising P-type devices responsive to enabling and disabling signals for conducting signals to and from the memory storage elements only during the presence of read and write signals, and which are substantially immune to the effects of long term, low level radiation, thereby substantially increasing the reliability of solid-state memory cells. Also provided are means for generating a control signal having first and second levels and logic means responsive to said control signals of a first level to generate and supply said enabling signal to said P-type device and further responsive to said control signal of a second level to generate and supply said disabling signal to said P-type device. Sensing means for sensing the state of said bistable memory elements during a time period between successive level changes of said control signals is also provided.