Abstract: A graphical bitmap image of a scanned test pattern drawing is transformed into a test file in a file format that is readily usable to provide stimuli for computer-aided design (CAD) tools or integrated circuit (IC) testing equipment. A bitmap image of each page of the test pattern drawing is produced as a graphical image of the rows and columns of test pattern data. Non-essential drawing symbols are then removed from the bitmap image, such as the lines used to draw the table. Essential test pattern information is recognized and is converted into a machine readable format by first storing the data in a tabular format having rows and columns which correspond to the rows and columns of the test pattern drawing. The stored test pattern data is then integrated with a machine readable file format which is adaptable to the CAD and IC tool in order to produce the machine readable test file.

Abstract: A VHSIC hardware description language model is generated from a scanned image of an electronic circuit by: a.

Abstract: The processing time and memory in converting scanned images to a hardware scription language is significantly reducer by using a "peephole" method to examine only partial images of features of the scanned image that is to be converted. The present method generated minimized feature templates (MFTs) by systematically removing all non-feature image pixels. In particular, the method and apparatus of the present invention establishes pattern estimates from image samples, eliminates unnecessary image pixels using off-line statistical analysis, and extracts feature templates from the larger size image patterns. Pattern recognition is then conducted by processing a few pixels of the unknown image pattern. An application of this technique is to recognize drawing symbols, such as, AND, NAND, OR, NOR, XOR, and XNOR gates, buffers, inverters, registers, and I/O pins from scanned images of electronic drawings.

Abstract: A digital microelectronic replacement package includes at least one buffer die in combination with a programmable device or memory. The buffer die performs the functions of impedance-matching, delay-matching, and voltage-matching, while the programmable device or memory can be used to emulate the logic and/or storage functions of the original digital microelectronic circuit; the package of the invention can be used as a direct replacement for a digital microelectronic circuit without the requirement that the original circuit board be redesigned to accommodate modern voltage, impedance, and delay specifications associated with the programmable device or memory.

Abstract: A built-in self test method and circuit identifies a faulty integrated ciit chip in a multichip module. The built-in self test method first applies a test pattern to a multichip module having a plurality of integrated circuit chips and to a reference signal generator, generates a first and second reference signal representing test responses for a fault free multichip module, compresses the outputs from the multichip module into a first and second bit using a first and second linear space compressor, uses exclusive OR logic to combine the first bit with the first reference signal to produce a first fault detection output and to combine the second bit with the second reference signal to produce a second fault detection output, stores the first and second fault detection outputs in a pair of N-bit shift registers; compares the stored outputs to detect a fault condition, and applies a series of recursive logic operations to identify the faulty integrated circuit chip in the multichip module.

Abstract: Apparatus for providing a direct indication of the failure of an electronic ircuit including a built-in self test circuit which performs an initial test on the electronic circuit and having a visual indicator coupled thereto which becomes activated when the self test circuit senses a failure of the electronic circuit upon power being supplied thereto or during operation. The electronic circuit with the built-in test feature consists of an integrated circuit chip or a multi-chip module encapsulated in a package with the indicator means visible therethrough. The indicator consists either of a light emitting diode or fusible material which changes its appearance and becomes visible through the package upon being activated by the built-in self test circuit.