Patents by Inventor Gerald W Gibson, Jr.
Gerald W Gibson, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7981305Abstract: A method for forming high density emission elements and field emission displays formed according to the method. Oxygen and a silicon etchant are introduced into a plasma etching chamber containing a silicon substrate. The oxygen reacts with the silicon surface to form regions of silicon dioxide, while the silicon etchant etches the silicon to form the emission elements. The silicon dioxide regions mask the underlying silicon during the silicon etch process. High density and high aspect ratio emission elements are formed without using photolithographic processes. The emission elements formed according to the present invention provide a more uniform emission of electrons. Further, a display incorporating emission elements formed according to the present invention provides increased brightness. The reliability of the display is increased due to the use of a plurality of emission elements to supply electrons for stimulating the phosphor substrate material to produce the image.Type: GrantFiled: July 20, 2009Date of Patent: July 19, 2011Assignee: Agere Systems Inc.Inventors: Seong Jin Koh, Gerald W. Gibson, Jr.
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Patent number: 7632690Abstract: A process and apparatus for controlling an etchant gas concentration in an etch chamber. The etchant gas concentration and an inert gas concentration are determined and the latter concentration is used to normalize the etchant gas concentration. The normalized value is compared with a predetermined reference value and the flow of etchant gas into the chamber is controlled in response thereto.Type: GrantFiled: July 13, 2007Date of Patent: December 15, 2009Assignee: Agere Systems Inc.Inventor: Gerald W. Gibson, Jr.
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Publication number: 20090280585Abstract: A method for forming high density emission elements and field emission displays formed according to the method. Oxygen and a silicon etchant are introduced into a plasma etching chamber containing a silicon substrate. The oxygen reacts with the silicon surface to form regions of silicon dioxide, while the silicon etchant etches the silicon to form the emission elements. The silicon dioxide regions mask the underlying silicon during the silicon etch process. High density and high aspect ratio emission elements are formed without using photolithographic processes. The emission elements formed according to the present invention provide a more uniform emission of electrons. Further, a display incorporating emission elements formed according to the present invention provides increased brightness. The reliability of the display is increased due to the use of a plurality of emission elements to supply electrons for stimulating the phosphor substrate material to produce the image.Type: ApplicationFiled: July 20, 2009Publication date: November 12, 2009Applicant: Agere Systems Inc.Inventors: Seong Jin Koh, Gerald W. Gibson, JR.
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Patent number: 7564178Abstract: A method for forming high density emission elements for a field emission display and field emission elements and field emission displays formed according to the method. Oxygen and a silicon etchant are introduced into a plasma etching chamber containing a silicon substrate. The oxygen reacts with the silicon surface to form regions of silicon dioxide, while the silicon etchant etches the silicon to form the emission elements. The silicon dioxide regions mask the underlying silicon during the silicon etch process. High density and high aspect ratio emission elements are formed without using photolithographic processes as practiced in the prior art. The emission elements formed according to the present invention provide a more uniform emission of electrons than the prior art techniques. Further, a display incorporating emission elements formed according to the present invention provides increased brightness.Type: GrantFiled: February 14, 2005Date of Patent: July 21, 2009Assignee: Agere Systems Inc.Inventors: Seong Jin Koh, Gerald W. Gibson, Jr.
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Patent number: 7332775Abstract: A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous carbon sacrificial layer as the top layer of the patterned gate electrode structure. Dielectric spacers are formed alongside the gate electrode structure, including alongside the sacrificial amorphous carbon layer. The dielectric spacers extend substantially to the top of the amorphous carbon layer. The amorphous carbon layer is then removed such that the remaining gate structure includes dielectric spacers that have a protruding section that protrudes above the top surface of the remaining gate structure. A nitride layer may be formed over the gate structure. Such a structure prevents exposure of the gate electrode during the formation of self-aligned contacts, and shorting, once the contact openings are filled.Type: GrantFiled: October 4, 2006Date of Patent: February 19, 2008Assignee: Agere Systems Inc.Inventors: Kurt George Steiner, Gerald W. Gibson, Jr., Eduardo Jose Quinones
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Patent number: 7261745Abstract: A process and apparatus for controlling an etchant gas concentration in an etch chamber. The etchant gas concentration and an inert gas concentration are determined and the latter concentration is used to normalize the etchant gas concentration. The normalized value is compared with a predetermined reference value and the flow of etchant gas into the chamber is controlled in response thereto.Type: GrantFiled: September 30, 2003Date of Patent: August 28, 2007Assignee: Agere Systems Inc.Inventor: Gerald W. Gibson, Jr.
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Patent number: 7126198Abstract: A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous carbon sacrificial layer as the top layer of the patterned gate electrode structure. Dielectric spacers are formed alongside the gate electrode structure, including alongside the sacrificial amorphous carbon layer. The dielectric spacers extend substantially to the top of the amorphous carbon layer. The amorphous carbon layer is then removed such that the remaining gate structure includes dielectric spacers that have a protruding section that protrudes above the top surface of the remaining gate structure. A nitride layer may be formed over the gate structure. Such a structure prevents exposure of the gate electrode during the formation of self-aligned contacts, and shorting, once the contact openings are filled.Type: GrantFiled: September 3, 2002Date of Patent: October 24, 2006Assignee: Agere Systems Inc.Inventors: Kurt George Steiner, Gerald W. Gibson, Jr., Eduardo Jose Quinones
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Patent number: 7087498Abstract: A method for forming a trench in a semiconductor silicon substrate. An anti-reflective coating layer and a photoresist layer are formed over the substrate and patterned in accordance with a location for the trench. During the trench etch into the silicon substrate, the etch environment is monitored to detect the material of the anti-reflective coating layer. The etch process is controlled in response to detecting the removal of this material and the known etch rate differential between the anti-reflective coating material layer and the silicon substrate.Type: GrantFiled: September 30, 2003Date of Patent: August 8, 2006Assignee: Agere Systems Inc.Inventors: Mario Pita, Milton Beachy, Gerald W. Gibson, Jr.
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Patent number: 6879046Abstract: A split barrier layer enables copper interconnect wires to be used in conjunction with low-k dielectric films by preventing the diffusion of N—H base groups into photoresists where they can render the photoresist insoluble. The split barrier layer is disposed between the copper and the low-k dielectric and includes a nitrogen-containing, oxygen-free film which contacts the copper, and an oxygen-containing, nitrogen-free film which contacts the low-k dielectric film. The nitrogen-containing film prevents the formation of undesirable copper oxides, and the oxygen-containing film prevents the diffusion of N—H base groups into the low-k dielectric films. The oxygen-containing film may be an oxygen-doped silicon carbide film in an exemplary embodiment. In another embodiment, a film stack of low-k dielectric films includes an etch-stop layer and hardmask each formed of oxygen-doped silicon carbide.Type: GrantFiled: January 2, 2002Date of Patent: April 12, 2005Assignee: Agere Systems Inc.Inventors: Gerald W Gibson, Jr., Scott Jessen, Steven Alan Lytle, Kurt George Steiner, Susan Clay Vitkavage
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Patent number: 6362094Abstract: The present invention provides a method of fabricating a self-aligning contact opening comprising: (a) forming a dielectric layer over a semiconductor substrate and gate electrodes located on the semiconductor substrate, (b) forming a carbide liner over the dielectric layer, and (c) etching at least a portion the carbide liner to form a self-aligning contact opening between the gate electrodes.Type: GrantFiled: August 16, 2000Date of Patent: March 26, 2002Assignee: Agere Systems Guardian Corp.Inventors: Gary Dabbaugh, Gerald W. Gibson, Jr., Troy A. Giniecki, Kurt G. Steiner
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Patent number: 6110395Abstract: The present invention relates to a method and structure for controlling plasma uniformity in plasma processing applications. Electron thermal conductivity parallel and perpendicular to magnetic field lines differs by orders of magnitude for low magnetic fields (on the order of 10 gauss). This property allows the directing of heat flux by controlling the magnetic field configuration independent of ions since the effect of modest magnetic fields upon the transport of ions themselves is minimal. Heat is preferentially conducted along magnetic field lines with electron temperatures on the order of 0.1 to 1 eV/cm being sufficient to drive kilowatt-level heat fluxes across areas typical of plasma processing source dimensions.Type: GrantFiled: August 26, 1997Date of Patent: August 29, 2000Assignee: Trikon Technologies, Inc.Inventor: Gerald W. Gibson, Jr.