Abstract: The high speed operational recurring signature evaluation provides digital sub-systems including a data compressor and a controller. These subsystems are employed with a portable service processor (PSP) which is a standard piece of test equipment in this art. The controller interfaces with the host logic tester (PSP) to provide the repetitious detail and complex digital control requirements for programming the data compressor in response to digital instructions received from the logic tester. A unique serial data pattern corresponding to a proper signature from a node under test generated in real time at the relatively high operating speed of the board under test is generated by the data compressor.