Patents by Inventor Gerald W. Jones
Gerald W. Jones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6887779Abstract: A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.Type: GrantFiled: November 21, 2003Date of Patent: May 3, 2005Assignee: International Business Machines CorporationInventors: David J. Alcoe, Francis J. Downes, Jr., Gerald W. Jones, John S. Kresge, Cheryl L. Tytran-Palomaki
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Patent number: 6829823Abstract: A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors.Type: GrantFiled: February 5, 2002Date of Patent: December 14, 2004Assignee: International Business Machines CorporationInventors: Francis J. Downes, Jr., Donald S. Farquhar, Elizabeth Foster, Robert M. Japp, Gerald W. Jones, John S. Kresge, Robert D. Sebesta, David B. Stone, James R. Wilcox
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Publication number: 20040099939Abstract: A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.Type: ApplicationFiled: November 21, 2003Publication date: May 27, 2004Inventors: David J. Alcoe, Francis J. Downes, Gerald W. Jones, John S. Kresge, Cheryl L. Tytran-Palomaki
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Patent number: 6720502Abstract: A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.Type: GrantFiled: May 15, 2000Date of Patent: April 13, 2004Assignee: International Business Machine CorporationInventors: David J. Alcoe, Francis J. Downes, Jr., Gerald W. Jones, John S. Kresge, Cheryl L. Tytran-Palomaki
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Patent number: 6593534Abstract: A structure of and method for producing a multilayer printed or wiring circuit board, and more particularly a method producing so-called z-axis or multilayer electrical interconnections in a hierarchial wiring structure in order to be able to provide for an increase in the number of inputs and outputs (I/O) in comparison with a standard printed wiring board (PWB) arrangement, and a printed wiring board produced by the method.Type: GrantFiled: March 19, 2001Date of Patent: July 15, 2003Assignee: International Business Machines CorporationInventors: Gerald W. Jones, John M. Lauffer, Voya R. Markovich, Thomas R. Miller, James P. Paoletti, Konstantinos I. Papathomas, James R. Stack
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Publication number: 20020131229Abstract: A structure of and method for producing a multilayer printed or wiring circuit board, and more particularly a method producing so-called z-axis or multilayer electrical interconnections in a hierarchial wiring structure in order to be able to provide for an increase in the number of inputs and outputs (I/O) in comparison with a standard printed wiring board (PWB) arrangement, and a printed wiring board produced by the method.Type: ApplicationFiled: March 19, 2001Publication date: September 19, 2002Applicant: International Business Machines CorporationInventors: Gerald W. Jones, John M. Lauffer, Voya R. Markovich, Thomas R. Miller, James P. Paolletti, Konstantinos I. Papathomas, James R. Stack
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Patent number: 6447914Abstract: The present invention comprises a method of making a circuitized structure. The method comprises the steps of providing a substrate coated with a polymeric dielectric layer, treating the substrate with alkali, baking the substrate to modify the surface of the polymeric dielectric layer, applying a seed layer to the polymeric dielectric layer and applying conductive layer to the seed layer. The invention also comprises a printed circuit structure produced by the method of the present invention.Type: GrantFiled: July 3, 2000Date of Patent: September 10, 2002Assignee: International Business Machines CorporationInventors: Anastasios P. Angelopoulos, Gerald W. Jones, Luis J. Matienzo, Thomas R. Miller, William D. Taylor
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Patent number: 6420253Abstract: A method and structure is provided for preventing wetting or bleed of an adhesive, such as an epoxy, onto noble metal wire bond pads on the surface of a dielectric substrate when attaching an I/C chip to the substrate. The method includes treating the wire bond pads with a chemical composition which prevents bleeding onto the surfaces of the wire bond pads by a component of the epoxy. The chemical composition is a chemical which will provide “Self-Assembled Monolayers” (SAMs) on the surface of the gold. These compositions are characterized by a molecule having at least one group, such as a mercaptan or disulfide, connected to a hydrocarbon moiety, such as a (CH2)x chain. The affinity of the thiol or sulfur-containing portion of the molecule chemically bonding with the noble metal provides a relatively strong attachment of the molecule to the metal surface.Type: GrantFiled: June 14, 2001Date of Patent: July 16, 2002Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, Gary A. Johansson, Gerald W. Jones, Luis J. Matienzo, Yenloan H. Nguyen, Konstantinos I. Papathomas
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Publication number: 20020085364Abstract: An electronic package, and method of making the electronic package, is provided. The package includes a semiconductor chip and an multi-layered interconnect structure having a high density interconnect layer such as an allylated surface layer. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip.Type: ApplicationFiled: February 5, 2002Publication date: July 4, 2002Inventors: Francis J. Downes, Donald S. Farquhar, Elizabeth Foster, Robert M. Japp, Gerald W. Jones, John S. Kresge, Robert D. Sebesta, David B. Stone, James R. Wilcox
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Patent number: 6373717Abstract: An electronic package, and method of making the electronic package, is provided. The package includes a semiconductor chip and an multi-layered interconnect structure having a high density interconnect layer such as an allylated surface layer. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip.Type: GrantFiled: March 31, 2000Date of Patent: April 16, 2002Assignee: International Business Machines CorporationInventors: Francis J. Downes, Jr., Donald S. Farquhar, Elizabeth Foster, Robert M. Japp, Gerald W. Jones, John S. Kresge, Robert D. Sebesta, David B. Stone, James R. Wilcox
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Publication number: 20010028117Abstract: A method and structure is provided for preventing wetting or bleed of an adhesive, such as an epoxy, onto noble metal wire bond pads on the surface of a dielectric substrate when attaching an I/C chip to the substrate. The method includes treating the wire bond pads with a chemical composition which prevents bleeding onto the surfaces of the wire bond pads by a component of the epoxy. The chemical composition is a chemical which will provide “Self-Assembled Monolayers” (SAMs) on the surface of the gold. These compositions are characterized by a molecule having at least one group, such as a mercaptan or disulfide, connected to a hydrocarbon moiety, such as a (CH2)x chain. The affinity of the thiol or sulfur-containing portion of the molecule chemically bonding with the noble metal provides a relatively strong attachment of the molecule to the metal surface.Type: ApplicationFiled: June 14, 2001Publication date: October 11, 2001Applicant: International Business Machines CorporationInventors: Bernd K. Appelt, Gary A. Johansson, Gerald W. Jones, Luis J. Matienzo, Yenloan H. Nguyen, Konstantinos I. Papathomas
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Patent number: 6252307Abstract: A method and structure is provided for preventing wetting or bleed of an adhesive, such as an epoxy, onto noble metal wire bond pads on the surface of a dielectric substrate when attaching an I/C chip to the substrate. The method includes treating the wire bond pads with a chemical composition which prevents bleeding onto the surfaces of the wire bond pads by a component of the epoxy. The chemical composition is a chemical which will provide “Self-Assembled Monolayers” (SAMs) on the surface of the gold. These compositions are characterized by a molecule having at least one group, such as a mercaptan or disulfide, connected to a hydrocarbon moiety, such as a (CH2)x chain. The affinity of the thiol or sulfur-containing portion of the molecule chemically bonding with the noble metal provides a relatively strong attachment of the molecule to the metal surface.Type: GrantFiled: March 28, 2000Date of Patent: June 26, 2001Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, Gary A. Johansson, Gerald W. Jones, Luis J. Matienzo, Yenloan H. Nguyen, Konstantinos I. Papathomas
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Patent number: 6136513Abstract: The present invention comprises a method of making a circuitized structure. The method comprises the steps of providing a substrate coated with a polymeric dielectric layer, treating the substrate with alkali, baking the substrate to modify the surface of the polymeric dielectric layer, applying a seed layer to the polymeric dielectric layer and applying a conductive layer to the seed layer. The invention also comprises a printed circuit structure produced by the method of the present invention.Type: GrantFiled: April 23, 1998Date of Patent: October 24, 2000Assignee: International Business Machines CorporationInventors: Anastasios P. Angelopoulos, Gerald W. Jones, Luis J. Matienzo, Thomas R. Miller, William D. Taylor
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Patent number: 5599747Abstract: A method of making a circuitized substrate which may be utilized as a chip carrier structure. The method involves the steps of providing a dielectric member and partially routing this member to define a temporary support portion therein. Metallization and circuitization may then occur, following which the temporary support portion is removed. This temporary support thus assures effective support for the photoresist used as part of the circuitization process. Thus, the photoresist is capable of being applied in sheetlike form for spanning the relatively small openings of the dielectric without sagging, bowing, etc., which may adversely impact subsequent processing steps.Type: GrantFiled: June 27, 1995Date of Patent: February 4, 1997Assignee: International Business Machines CorporationInventors: Ashwinkumar C. Bhatt, Thomas P. Duffy, David E. Houser, Gerald W. Jones, Jeffrey McKeveny, Kenneth L. Potter
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Patent number: 5460921Abstract: The present invention provides a method of ablative photodecomposition and forming metal pattern which attains high resolution, is convenient, and employs non-halogenated solvents. The present invention is directed to a process for forming a metal pattern, preferably circuitization on an organic substrate, preferably on a circuit board or component thereof, which comprises coating the substrate with an ablatively-removable coating comprising a polymer resin preferably an acrylate polymer resin and preferably an ultraviolet absorber. A pattern is formed in the polymer coating corresponding to the desired metal pattern by irradiating at least a portion of the polymer coating with a sufficient amount of ultraviolet radiation to thereby ablatively remove the irradiated portion of the polymer coating. Next the patterned substrate is coated with a conductive metal paste to define the metal pattern, and the conductive metal paste is cured.Type: GrantFiled: September 8, 1993Date of Patent: October 24, 1995Assignee: International Business Machines CorporationInventors: Douglas A. Cywar, Charles R. Davis, Thomas P. Duffy, Frank D. Egitto, Paul J. Hart, Gerald W. Jones, Edward McLeskey
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Patent number: 5268260Abstract: Simple, environmentally friendly developers and strippers are disclosed for free radical-initiated, addition polymerizable resists, cationically cured resists and solder masks and Vacrel photoresists. In all cases both the developers and the strippers include gamma butyrolactone, propylene carbonate and benzyl alcohol, optionally also including a minor amount of methanol, ethanol, isopropyl alcohol, propylene glycol monomethylacetate, ethylene glycol monomethyl ether, formamide, nitromethane, propylene oxide, or methyl ethyl ketone, acetone and water.Type: GrantFiled: October 22, 1991Date of Patent: December 7, 1993Assignee: International Business Machines CorporationInventors: Nageshwer R. Bantu, Anilkumar C. Bhatt, Ashwinkumar C. Bhatt, Joseph A. Kotylo, Gerald W. Jones, Robert J. Owen, Kostas Papathomas, Anaya K. Vardya
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Patent number: 4956197Abstract: A dielectric surface is conditioned for electroless plating of a conductive metal thereon by exposing the substrate to a gaseous plasma obtained from ammonia and/or an organic amine. The conditioning can be in the holes and/or on the surfaces of the substrate.Type: GrantFiled: September 30, 1988Date of Patent: September 11, 1990Assignee: International Business Machines CorporationInventors: Suryadevara V. Babu, Neng-Hsing Lu, Gerald W. Jones
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Patent number: 4697923Abstract: A method is disclosed for the visual inspection of electrical circuitry deposited in the layers of a multilayer printed circuit board wherein the dielectric layers of the multilayer board are prepared using a clear, light transparent thermosetting resin having incorporated therein a dye which is permeable to visible light but which absorbs light in the 320-440 nm region.The electrical circuitry in the board can be easily traced by an observer upon illumination of the board by visible light.Type: GrantFiled: March 25, 1986Date of Patent: October 6, 1987Assignee: IBM CorporationInventors: Gerald W. Jones, W. Robert Pratt, William J. Summa