Patents by Inventor Gerard A. Kreifels
Gerard A. Kreifels has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11442807Abstract: The present disclosure includes apparatuses and methods for ECC operation associated with memory. One example apparatus comprises a controller configured to perform an error correction code (ECC) operation on a codeword stored in the memory, wherein the codeword includes a first number of ECC bits and the first number of ECC bits are generated based on an encoding matrix, wherein each row of the encoding matrix has an odd number of bits having a binary value of 1.Type: GrantFiled: January 25, 2021Date of Patent: September 13, 2022Assignee: Micron Technology, Inc.Inventor: Gerard A. Kreifels
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Publication number: 20210141690Abstract: The present disclosure includes apparatuses and methods for ECC operation associated with memory. One example apparatus comprises a controller configured to perform an error correction code (ECC) operation on a codeword stored in the memory, wherein the codeword includes a first number of ECC bits and the first number of ECC bits are generated based on an encoding matrix, wherein each row of the encoding matrix has an odd number of bits having a binary value of 1.Type: ApplicationFiled: January 25, 2021Publication date: May 13, 2021Inventor: Gerard A. Kreifels
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Patent number: 10949300Abstract: Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node.Type: GrantFiled: October 30, 2019Date of Patent: March 16, 2021Assignee: Micron Technology, Inc.Inventors: Yihua Zhang, Paolo E. Mangalindan, Jianfei Lei, Andrew D. Proescholdt, Gerard A. Kreifels
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Patent number: 10901837Abstract: The present disclosure includes apparatuses and methods for ECC operation associated with memory. One example apparatus comprises a controller configured to perform an error correction code (ECC) operation on a codeword stored in the memory, wherein the codeword includes a first number of ECC bits and the first number of ECC bits are generated based on an encoding matrix, wherein each row of the encoding matrix has an odd number of bits having a binary value of 1.Type: GrantFiled: December 13, 2018Date of Patent: January 26, 2021Assignee: Micron Technology, Inc.Inventor: Gerard A. Kreifels
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Publication number: 20200073754Abstract: Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node.Type: ApplicationFiled: October 30, 2019Publication date: March 5, 2020Inventors: Yihua Zhang, Paolo E. Mangalindan, Jianfei Lei, Andrew D. Proescholdt, Gerard A. Kreifels
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Patent number: 10496475Abstract: Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node.Type: GrantFiled: July 9, 2018Date of Patent: December 3, 2019Assignee: Micron Technology, Inc.Inventors: Yihua Zhang, Paolo E. Mangalindan, Jianfei Lei, Andrew D. Proescholdt, Gerard A. Kreifels
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Publication number: 20190129791Abstract: The present disclosure includes apparatuses and methods for ECC operation associated with memory. One example apparatus comprises a controller configured to perform an error correction code (ECC) operation on a codeword stored in the memory, wherein the codeword includes a first number of ECC bits and the first number of ECC bits are generated based on an encoding matrix, wherein each row of the encoding matrix has an odd number of bits having a binary value of 1.Type: ApplicationFiled: December 13, 2018Publication date: May 2, 2019Inventor: Gerard A. Kreifels
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Patent number: 10176040Abstract: The present disclosure includes apparatuses and methods for ECC operation associated with memory. One example apparatus comprises a controller configured to perform an error correction code (ECC) operation on a codeword stored in the memory, wherein the codeword includes a first number of ECC bits and the first number of ECC bits are generated based on an encoding matrix, wherein each row of the encoding matrix has an odd number of bits having a binary value of 1.Type: GrantFiled: April 5, 2016Date of Patent: January 8, 2019Assignee: Micron Technology, Inc.Inventor: Gerard A. Kreifels
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Publication number: 20180314593Abstract: Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node.Type: ApplicationFiled: July 9, 2018Publication date: November 1, 2018Inventors: Yihua Zhang, Paolo E. Mangalindan, Jianfei Lei, Andrew D. Proescholdt, Gerard A. Kreifels
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Patent number: 10067827Abstract: Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node.Type: GrantFiled: June 29, 2016Date of Patent: September 4, 2018Assignee: MICRON TECHNOLOGY, INC.Inventors: Yihua Zhang, Paolo E. Mangalindan, Jianfei Lei, Andrew D. Proescholdt, Gerard A. Kreifels
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Publication number: 20180004596Abstract: Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node.Type: ApplicationFiled: June 29, 2016Publication date: January 4, 2018Inventors: Yihua Zhang, Paolo E. Mangalindan, Jianfei Lei, Andrew D. Proescholdt, Gerard A. Kreifels
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Publication number: 20170286217Abstract: The present disclosure includes apparatuses and methods for ECC operation associated with memory. One example apparatus comprises a controller configured to perform an error correction code (ECC) operation on a codeword stored in the memory, wherein the codeword includes a first number of ECC bits and the first number of ECC bits are generated based on an encoding matrix, wherein each row of the encoding matrix has an odd number of bits having a binary value of 1.Type: ApplicationFiled: April 5, 2016Publication date: October 5, 2017Inventor: Gerard A. Kreifels
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Patent number: 8601202Abstract: Methods and systems to wear level a non-volatile memory device across partitions. In an embodiment, a memory device performs background operations to swap host addressable memory partitions with a spare memory partition outside of the host address space. In one embodiment, the background inter-partition wear leveling operations are appended to a user erase operations.Type: GrantFiled: August 26, 2009Date of Patent: December 3, 2013Assignee: Micron Technology, Inc.Inventors: Robert Melcher, Sean Eilert, Gerard Kreifels
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Publication number: 20060282643Abstract: In high-density mode, data may be stored in consecutive byte blocks. In low-density mode, a codeword of memory space may have the capacity to store two bytes of data, but may be used to store only a single byte of data. In a multi-level cell architecture where two or more bits may be stored in a single cell, memory address translation circuitry (or other system component) may translate data to be stored in low-density mode. Memory address translation circuitry may adjust the bit ordering of data to be stored to compensate for the consequences of low-density mode. A single flash memory device may have data stored in one portion in low-density mode and data stored in another portion in high-density mode. Error correcting code (ECC) may be applied in high-density mode and not in low-density mode.Type: ApplicationFiled: June 10, 2005Publication date: December 14, 2006Inventors: Subramanyam Chandramouli, Gerard Kreifels, Bharat Pathak, Edward Babb
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Patent number: 4891788Abstract: An almost full flag for a FIFO includes first and second counters for determining the proximity of the Read and Write pointers in the FIFO. A compare circuit is provided for comparing the output of the counters to determine when the count values are separated by a predetermined value. When the separation is equal to the predetermined value, the output of the comparitor goes low. A half flag is set when a Write operation occurs and the difference value between the Read and Write pointers increases. The set operation is performed in response to the presence of the compare signal at a low logic state at the time that the Write operation occurs, thus eliminating any delays in generating a transition in the compare circuit. The flag is reset when the compare signal is at the low logic state. Blanking circuitry is provided for blanking the reset operation when a Read operation occurs and the output of the comparator makes a transition from the first logic state to the second logic state.Type: GrantFiled: July 11, 1989Date of Patent: January 2, 1990Inventor: Gerard A. Kreifels