Abstract: An apparatus for speculatively forwarding storehit data in a microprocessor pipeline. First and second virtual address comparators compare a virtual load address with first and second virtual store addresses to generate a virtual match signal for indicating whether first and second storehit data is likely present in a store buffer and a result forwarding cache, respectively. If the first and second storehit data are both present the second storehit data is newer than the first storehit data. First and second physical address comparators compare a physical load address translated from the virtual load address with first and second physical store addresses translated from the plurality of virtual store addresses to generate a physical match signal for indicating whether the first and second storehit data is certainly present in the store buffer and the result forwarding cache, respectively.

Abstract: A method and apparatus are provided for writing to a flags register in a pipeline microprocessor. Responsive to a macro instruction that directs a write to the flags register, a mask is generated using destination information for the write and privilege level information for the write. The mask is then ANDed with new values for bits within the flags register and the result is written to the flags register in a single instruction cycle.

Abstract: A method and apparatus are provided for reading from and storing a flags register in a processor. In response to a macro instruction directing the read and store operation, such as a push flags macro instruction, a mask is generated using privilege level information (i.e., current operating privilege level) to specify those bits of the flags register that can be stored.r. The mask is then ANDed with contents of the flags register to yield a result and the result is stored on a stack in memory.

Abstract: A method and apparatus are provided for processing far jump-call branch instructions within a processor in a manner which reduces the number of stalls of the processor pipeline. The processor includes an apparatus, for providing a fallback far jump-call speculative target address that corresponds to a current far jump-call branch instruction. The microprocessor apparatus includes a far jump-call branch target buffer and a fallback speculative target address generator. The far jump-call branch target buffer stores a plurality of code segment bases and offsets corresponding to a plurality of previously executed far jump-call branch instructions, and determines if a hit for the current far jump-call branch instruction is contained therein. The fallback speculative target address generator is coupled to the far jump-call branch target buffer.

Abstract: An apparatus and method for providing early instruction results is disclosed. Early execution logic, comprising an enhanced address generator located in an address generation stage of the microprocessor pipeline, receives input operands and generates early results of instructions reaching the address stage prior to final execution units (in lower pipeline stages) generating final results of the instruction for updating an architected register file. The early execution logic is configured to execute only a subset of the instructions in the microprocessor instruction set. The early results are invalid if the instruction is not in the subset. An early register file corresponding to the architected register file stores the early results and also provides the early results to the early execution logic as input operands. The generated early results are invalid if any input operands are invalid. Early status flags accumulated from the early results enable selective early execution of conditional instructions.

Abstract: A microprocessor apparatus is provided for performing a pop-compare operation. The microprocessor apparatus includes paired operation translation logic, load logic, and execution logic. The paired operation translation logic receives a macro instruction that prescribes the pop-compare operation, and generates a pop-compare micro instruction. The pop-compare micro instruction directs pipeline stages in a microprocessor to perform the pop-compare operation. The load logic is coupled to the paired operation translation logic. The load logic receives the pop-compare micro instruction, and retrieves a first operand from an address in memory, where the address is specified by contents of a register. The register is prescribed by the pop-compare micro instruction. The execution logic is coupled to the load logic. The execution logic receives the first operand, and compares the first operand to a second operand.

Abstract: A method and apparatus are provided for processing repeat string instructions with increased efficiency in a processor pipeline. Rather than explicitly generating an initial count register setup micro instruction each time a repeat (REP) prefix in encountered, the processor includes a shadow ECX register operating in parallel with an architectural ECX count register. This enables the contents of the architectural ECX register, which are also stored in the shadow ECX register, to be immediately transferred to an internal count register from the shadow ECX register upon the first iteration of a repeat string micro code sequence.

Abstract: A method and apparatus are provided for processing far jump-call branch instructions to increase the efficiency of a processor pipeline. The processor includes a far jump-call target buffer which stores the default address/operand size corresponding to each of a plurality of previously executed far jump-call instructions. When a far jump-call instruction is encountered, it is speculatively executed using the corresponding default address/operand size for that instruction as stored in the far jump-call target buffer. This speculative far jump-call instruction is executed and resolved thus determining the actual address/operand size. If the actual address/operand size matches the speculative default address/operand size then the speculation was correct and processing continues. However, if there is no match, then the speculation was wrong and the pipeline is flushed.

Abstract: An apparatus and method are provided for executing a push all/pop all instruction in a pipeline microprocessor. The apparatus includes an instruction buffer and a translator. The instruction buffer provides the push all/pop all instruction, directing the microprocessor to store/retrieve multiple operands to/from a stack. The translator generates a sequence of micro instructions to store/retrieve the multiple operands. Accesses to a pair of operands which are together aligned are combined into a single access.

Abstract: A method and apparatus for handling interrupts after transition of a mask flag is provided. In x86 processors, if the IF flag is set, interrupts are to be handled. However, if the IF flag transitions from a clear state to a set state, and the instruction which sets the IF bit is an STI instruction, then a pending interrupt is to be delayed for one instruction, unless the following instruction is a floating point instruction, and then the interrupt is to be handled immediately. The invention allows an interrupt to cause a branch to an exception handler if the IF bit is set. The exception handler determines whether the prior instruction was an STI instruction, and whether the prior state of the IF bit was clear. If both these conditions are true, the exception handler branches back to the main program. If either condition is not true, the exception handler branches to an interrupt service routine.

Abstract: A method and apparatus for handling interrupts after transition of a mask flag is provided. In x86 processors, if the IF flag is cleared, interrupts are to be masked. If the IF flag is set, interrupts are to be handled. However, if the IF flag transitions from a clear state to a set state, and the instruction which sets the IF bit is an STI instruction, then a pending interrupt is to be delayed for one instruction, unless the following instruction is a floating point instruction, and then the interrupt is to be handled immediately. The invention allows an interrupt to cause a branch to an exception handler if the IF bit is set. The exception handler determines whether the prior instruction was an STI instruction, and whether the prior state of the IF bit was clear. If both these conditions are true, the exception handler branches back to the main program. If either condition is not true, the exception handler branches to an interrupt service routine.