Abstract: Fault-tolerant synchronization of real-time equipment connected to a computer network of several tens of meters with an option of including or not including such equipment in the synchronization device is disclosed. Global scheduling of the real-time computer platform in the form of minor and major cycles is provided in order to reduce latency during sensor acquisition. The associated calculation and preparation of output to the actuator is provided in an integrated modular avionic (IMA) architecture. To achieve the foregoing, a synchronization bus separate from the data transfer network and circuits interfacing with this specific bus for processing the local real-time clocks in each piece of equipment in a fault-tolerant, decentralized manner is provided.

Abstract: This method enables the reconstitution of messages fragmented in packets. It comprises a process for taking a census of the packets made available to a terminal (1) by transmission networks (Na, Nb) and a process for the reassembling of messages from packets listed by the census-taking process. These two processes implement a table of pointers pointing at the packets made available to the terminal (1) by the transmission networks (Na, Nb), sorted out by membership message, said pointers being placed, for each membership message, in a stack according to the order in which the packets that they point at are made available to the terminal (1) and being provided with information or status fields enabling the reporting of doubles or discrepancies between the order in which the packets of a stack are made available and the natural order of the message fragments constituted by the payloads of the packets, and the fate of the packet pointed at during the reassembling process.

Abstract: The invention relates to the selection and sorting, by a device having access to one or more packet transmission networks, of the packets relating to it, from among the entirety of the packets made available by the networks, given that the packets respect at least two layers of protocols or even more.

Abstract: The invention relates to the selection and sorting, by an installation having access to one or more packet transmission networks, of the packets relating to it, from among the entirety of the packets made available by the networks, given that the packets respect at least two layers of protocols or even more.

Abstract: The invention enables fault-tolerant synchronization of real-time equipment connected to a computer network of several tens of meters with an option of including or not including such equipment in the synchronization device. It provides global scheduling of the real-time computer platform in the form of minor and major cycles in order to reduce latency during sensor acquisition, the associated calculation and preparation of output to the actuator in an integrated modular avionic (IMA) architecture. In order to do this, it uses a synchronization bus separate from the data transfer network and circuits interfacing with this specific bus for processing the local real-time clocks in each piece of equipment in a fault-tolerant, decentralized manner.

Abstract: This method enables the reconstitution of messages fragmented in packets. It comprises a process for taking a census of the packets made available to a terminal (1) by transmission networks (Na, Nb) and a process for the reassembling of messages from packets listed by the census-taking process. These two processes implement a table of pointers pointing at the packets made available to the terminal (1) by the transmission networks (Na, Nb), sorted out by membership message, said pointers being placed, for each membership message, in a stack according to the order in which the packets that they point at are made available to the terminal (1) and being provided with information or status fields enabling the reporting of doubles or discrepancies between the order in which the packets of a stack are made available and the natural order of the message fragments constituted by the payloads of the packets, and the fate of the packet pointed at during the reassembling process.

Abstract: A method for the reception and preprocessing of digital messages, with a view to their use by a handling processor. The method associates a tag identifying each message capable of being received with a descriptor of preprocessing operations to be applied to the message. The tag of certain messages is associated with a sequence of descriptors of instructions capable of being run. The descriptor is stored in a memory at an address calculated with the aid of the tag of the associated message. Upon reception of a message, the tag of the received message is read, the address of the descriptor is determined with the aid of the tag, the descriptor is read at the address thus calculated, and the instruction sequence associated with the tag of the message is run if the descriptor is of the instruction type.

Abstract: A processor for executing several functions. The processor has access to an addressable space including memories for program and for data and input/output registers. The method of operation includes the allocation of a right of access to each function, the dividing of the addressable space and of partitions, each associated with the access right of a function, and the dividing of the time of use of the processor into cyclic time slices associated with the access right of a function. At the start of each new time slice, it is confirmed that the processor has terminated the execution of the previous function. The method further includes the activation of the tasks of the corresponding function. During each access by a processor to an addressable area, the access right of the current time slice is compared with that associated with the accessed are, with an error signal being transmitted in case of an inconsistency.

Abstract: Method of processing several computer-controlled technical applications. The applications are executed within the same computer working in successive work cycles by allotting thereto during the work cycles at least one time slot of a previously fixed duration. At the end of the time slot allotted to a technical application, a start interrupt is generated which is aimed at starting the execution of another technical application. Each technical application has allotted thereto at least one memory space slot for writing data. The memory space slot is write-inaccessible to the other technical applications so that a technical application which during execution possesses a given level of criticality does not disturb another application having a higher or equal level of criticality.

Abstract: To establish communications between a plurality of functional modules installed in a local unit and at least one Ethernet type external, multiplexed, multi-transmitter and multi-receiver bus enabling communications with other local units, the device according to the invention comprises as many internal buses as there are functional modules of the local unit, each internal bus being of the multiplexed, multi-transmitter and multi-receiver type, complying with the format of the information elements travelling through the external bus, said functional modules being coupled to the internal buses so that access to each internal bus is controlled by only one module; and at least one coupling module designed to provide for the transfer of information elements between the internal buses and the external bus.

Abstract: In order to connect a computer comprising plural redundant processors to at least one digital data transfer bus, the interfacing device embodying the invention comprises: a means for synchronizing and comparing the transmission and reception requests respectively transmitted by the processors, and for triggering processing of a request when the latter has been transmitted by all the processors, a means for transferring the data blocks to be transmitted or received between a controller of said bus and the respective working memories of the processors, and a means for triggering the transfer of a data block if the latter is simultaneously at the output of all the processors, from one of the working memories to said bus controller, with a view to transmission thereof on said bus.