Abstract: Embodiments of the invention provide a system for supporting numerous multiplexed and demultiplexed T1 signals and additional Ethernet signals between two DS-3 signals. In an embodiment, the multiplexer device is housed within a single rack unit on a standard 19? or 23? rack. In a further embodiment, all T1, Ethernet, alarm driver, and power connections are made from the front of the multiplexer unit, allowing easier access to the device connections restricted spaces. In a further embodiment, the system provides redundancy for the T3, T1, and Ethernet circuits, allowing error remediation. The system may also allow error detection for the associated telecommunications network.

Abstract: An active filter used for the loop filter of a phase-lock loop has one input to the operational amplifier thereof connected to receive the output from a phase detector, and has the non-inverting input connected to receive a control signal from an override signal generator. Under normal operating conditions, the output from the override signal generator is such that it does not affect operation of the active filter and the filter operates as a standard loop filter. During abnormal operating conditions the output signal from the override signal generator is of such magnitude that it causes the operational amplifier and, hence, the filter to output the maximum voltage +V. The filter output is connected to one end of a pair of serially connected resistors which have the node connected to the control voltage input of the voltage control oscillator. The other end of the serially connected resistors is connected to the collector of a transistor.

Abstract: A self-checking pulse density analyzer includes substantially similar first and second threshold detection circuits, each of which have one input connected to receive incoming pulse information to be analyzed, and each of which provide the same binary signal state at a separate output terminal, when the pulse density reaches a predetermined level. Each output terminal is connected to a separate input terminal of a threshold equalizing circuit and to respective inputs of first and second gating circuits. The threshold equalizing circuit is activated by the binary signal from the faster acting threshold detection circuit to speed up the operation of the slower threshold detection circuit and, thus, minimize the difference in operating time betwee the two circuits. These two nearly simultaneous binary indications cause the first gating circuit to operate and, thus, provide a particular binary output signal indicative thereof.