Patents by Inventor Gerard Lebesnerais

Gerard Lebesnerais has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4395681
    Abstract: A system is disclosed for compensating for the offset voltage problem which occurs in certain types of differential amplifiers; a differential amplifier, in the form of an operational amplifier, is provided with two generators of input signals whose difference is to be amplified; further included is an offset voltage compensation loop comprising a comparator, an n-bit up/down counter and a digital analog converter means; the output of said means being connected to said generators of input signals so as to modulate the input signals; and said digital analog converter means including first and second n-1 bit digital analog converters.
    Type: Grant
    Filed: December 23, 1980
    Date of Patent: July 26, 1983
    Assignee: International Business Machines Corp.
    Inventors: Robert Hornung, Gerard Lebesnerais
  • Patent number: 4298401
    Abstract: An implanted resistor structure for semiconductor integrated circuit devices is formed by a double ion-implantation providing a high breakdown voltage resistor.
    Type: Grant
    Filed: November 19, 1979
    Date of Patent: November 3, 1981
    Assignee: International Business Machines Corp.
    Inventors: Jean-Paul Nuez, Gerard Lebesnerais
  • Patent number: 4263518
    Abstract: Arrangements are described for correcting the voltage coefficient of resistance (VCR) of resistors integral with a semiconductor body and, more particularly, for correcting the VCR of resistors implanted in a semi-conductor body. Resistors typically comprising a resistive region of a first conductivity type formed in an isolated layer of opposite conductivity type which isolated layer, in general, includes an epitaxial layer passivated by a dielectric layer. A metal layer is formed on the dielectric layer and covers, at least partially, the resistive layer. The metal layer is brought to a suitable potential to produce opposite variations in the resistance with respect to variations created by the epitaxial layer.
    Type: Grant
    Filed: June 7, 1979
    Date of Patent: April 21, 1981
    Assignee: International Business Machines Corporation
    Inventors: Daniel Ballatore, Francois Delaporte, Gerard Lebesnerais, Jean-Paul Nuez