Abstract: Methods of designing an integrated circuit and an apparatus for designing an integrated circuit are disclosed herein. In one embodiment, a method includes: (1) generating a block model of the integrated circuit according to a first timing budget, (2) developing a top level implementation of the integrated circuit according to the first timing budget, (3) determining a second timing budget for the integrated circuit based on the block model and (4) modifying the block model and the top level implementation employing the second timing budget to provide a progressive block model and a modified top level implementation.

Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values. The delay stage includes M parallel-coupled inverter stages. Each parallel-coupled inverter stage includes N pairs of stacked PMOS transistors and stacked NMOS transistors. The N transistor pairs have configurable source-drain node connections between a drain node and a source node of each transistor in the pair, wherein the selectable delay value corresponds to a configuration of the configurable source-drain node connections to adjust a delay value of each of the M inverter stages.

Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values. The delay stage includes M parallel-coupled inverter stages. Each parallel-coupled inverter stage includes N pairs of stacked PMOS transistors and stacked NMOS transistors. The N transistor pairs have configurable source-drain node connections between a drain node and a source node of each transistor in the pair, wherein the selectable delay value corresponds to a configuration of the configurable source-drain node connections to adjust a delay value of each of the M inverter stages.

Abstract: A system and method for clock optimization to achieve timing signoff in an electronic circuit and an EDA tool that embodies the system or the method. In one embodiment, the system includes: (1) a clock cell identifier/sorter configured to identify at least some clock cells in a clock network associated with an electronic circuit design and sort the cells according to breadth, (2) a slack analyzer associated with the clock cell identifier/sorter and configured to identify flops that are downstream of the cells and determine a worst setup and hold timing slack thereof and (3) a clock cell delay adjuster associated with the slack analyzer and configured to adjust delays of the cells subject to the worst setup and hold timing slack.

Abstract: A system and circuit for virtual power grid is disclosed. In one embodiment, a switch system for a virtual power grid includes a first transistor for connecting a power supply to a node of a virtual power grid for an isolated region of circuitry via the first transistor upon a receipt of a first control signal to turn on the first transistor. The switch system further includes a second transistor for connecting the power supply to the isolated region of circuitry via the second transistor upon a receipt of a second control signal to turn on the second transistor. In addition, the switch system includes a self-timed enable module for generating and forwarding the second control signal when a voltage level at the node of the virtual power grid which is charged by the power supply via the first transistor reaches a threshold voltage.

Abstract: A system and circuit for virtual power grid is disclosed. In one embodiment, a switch system for a virtual power grid includes a first transistor for connecting a power supply to a node of a virtual power grid for an isolated region of circuitry via the first transistor upon a receipt of a first control signal to turn on the first transistor. The switch system further includes a second transistor for connecting the power supply to the isolated region of circuitry via the second transistor upon a receipt of a second control signal to turn on the second transistor. In addition, the switch system includes a self-timed enable module for generating and forwarding the second control signal when a voltage level at the node of the virtual power grid which is charged by the power supply via the first transistor reaches a threshold voltage.

Abstract: A system and method for clock optimization to achieve timing signoff in an electronic circuit and an EDA tool that embodies the system or the method. In one embodiment, the system includes: (1) a clock cell identifier/sorter configured to identify at least some clock cells in a clock network associated with an electronic circuit design and sort the cells according to breadth, (2) a slack analyzer associated with the clock cell identifier/sorter and configured to identify flops that are downstream of the cells and determine a worst setup and hold timing slack thereof and (3) a clock cell delay adjuster associated with the slack analyzer and configured to adjust delays of the cells subject to the worst setup and hold timing slack.

Abstract: What is described is a method to reduce variations in signal delays along paths in a design of an integrated circuit by balancing wire widths. The method operates by performing a circuit simulation to determine simulated signal delays along the circuit paths based on first wire widths for a given circuit, then running a delay model analysis to calculate predicted signal delays along the circuit paths based on first wire widths for the given circuit. The method then calculates a correction difference between the predicted signal delays and the simulated signal delays, and derives delay targets from the correction difference. Finally, the method calculates second wire widths using the delay model analysis to meet the delay targets. Preferably, the signal delays are clock signal delays, the circuit simulation is a SPICE circuit simulation, and the delay model is an Elmore delay model. Also described is a system which includes a CPU and certain memory components for accomplishing the method.

Abstract: An arbiter that includes a phase comparator receiving two input signals. The outputs of the phase comparator are propagated to a first SR type flip-flop. The outputs of the first SR type flip-flop are propagated to a second SR type flip-flop. The outputs of the second SR type flip-flop indicate which of the two input. signals changed first. The phase comparator can enter a metastable state. The first flip-flop reduces the magnitude of signal swing away from the power supply rails caused by the metastable state. The second flip-flop prevents any signal swing away for a power supply rail is not propagated to an output.

Abstract: A system and method are provided for counting a number of clock cycles. In one embodiment, the system comprises a cascaded series of write latches and a cascaded series of erase latches. The output of each of the write latches is electrically coupled to a respective diverting multiplexer configured to divert a counting signal from the cascaded series of write latches to the cascaded series of erase latches. In order to count a specific number of cycles of the clock, one of the diverting multiplexers is set so as to divert a logical “1” advancing along the write latches into the erase latches. A specific number of clock cycles is counted by forcing a logical “1” to advance through a predetermined number of write and erase latches. Generally, the number of write and erase latches used to count a given number of clock cycles is even. Consequently, the present invention also includes an odd latch to enable the counting of an odd number of clock cycles.

Abstract: A system and method for actively deskewing synchronous clocks in a VLSI circuit by introducing a controllable delay unit within a local clock buffer within each of a number of circuit zones and applying a controllable delay at each of the local clock buffers in response to a phase comparison of clock signals from one or more adjacent clock zones. The system can be added to any of a number of various clock distribution networks on a VLSI circuit through the introduction of controllable clock zone buffers and localized phase comparators. By adjusting each localized clock buffer delay unit in response to measured clock signal phase differences from adjacent circuit zones, clock skew problems can be minimized across various clock zones on a VLSI circuit.

Abstract: A bidirectional electronic interface couples remote sensing security transducers such as fire and burglar monitoring devices to a computer such that the circuitry of the bidirectional electronic interface functions to both transmit signals from the remote sensing transducer to the computer for analysis and processing and transmit control and data information to remote control and monitoring stations. The computer scans the content of the bidirectional electronic interface for remote transducer information with the bidirectional electronic interface serving as a storage apparatus. The computer is programmed to respond to the information presented by the bidirectional electronic interface to initiate predetermined control and data recording functions for both direct activation of remote apparatus and for transmittal of control signals through the bidirectional electronic interface circuitry to remote apparatus.

Abstract: Tamper test signals of varying magnitude and polarity are randomly applied to electronic sensing circuits to determine integrity of the sensing circuits. A monitoring circuit measures the response of the sensing circuit to the applied tamper test signals and responds to deviations from predetermined information indicative of sensing circuit integrity by generating output signals suitable for control or alarm purposes.