Patents by Inventor Gerard M. Lebesnerais

Gerard M. Lebesnerais has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4578695
    Abstract: A monolithically integrated resistive attenuator is autobiased from an input bipolar signal the amplitude of which is higher than the integrated circuit voltage supplies. The resistive attenuator is arranged in a first pocket formed in an epitaxial layer, and is connected between the input bipolar signal and ground. An intermediate tap produces an output signal. A diode and capacitor are formed in a second pocket. The diode is connected between the input bipolar signals and the epitaxial layer while the capacitor is connected between the epitaxial layer and the isolation walls thereof. The positive half-periods of the input bipolar signal charges the capacitor, which in turn biases the epitaxial layers. The attenuator, therefore, can be monolithically integrated into a silicon chip and remain isolated for all values of the input bipolar signal.
    Type: Grant
    Filed: November 21, 1983
    Date of Patent: March 25, 1986
    Assignee: International Business Machines Corporation
    Inventors: Francois-Xavier Delaporte, Gerard M. Lebesnerais, Jean-Pierre Pantani
  • Patent number: 4348595
    Abstract: The basic circuit (FIG. 2) includes an input device (A) driving two output transistors (B) and (C) which have different rise times [injection currents (I2, I3) or the input characteristics of the transistors (capacitors C2, C3) may be adjusted]. In a preferred embodiment (FIG. 3) differentiation is ensured by coupling a control transistor D to one of the output transistors (B) through a PNP transistor. If transistors (B) and (C) are cross-coupled, the circuit which is achieved is a bistable device. FIG. 4 shows the layout of the circuit of FIG. 3. Various applications in the synchronous logic circuit domain are described: T flip-flop (FIG. 8) and shift register (FIG. 9).
    Type: Grant
    Filed: September 12, 1980
    Date of Patent: September 7, 1982
    Assignee: International Business Machines Corporation
    Inventor: Gerard M. Lebesnerais
  • Patent number: 4340922
    Abstract: An interface circuit for exchanging digital signals between two pieces of data processing equipment is provided in integrated form in accordance with international standards, such as EIA Standards. This is achieved through modification of an operational amplifier to adapt its use to the conditions and requirements of interface circuits.
    Type: Grant
    Filed: November 21, 1980
    Date of Patent: July 20, 1982
    Assignee: International Business Machines Corp.
    Inventors: Francois X. Delaporte, Gerard M. Lebesnerais, Jean-Pierre Pantani
  • Patent number: 4277701
    Abstract: Integrated Injection Logic (I.sup.2 L) Structures are disclosed. The disclosure includes integrated injection logic cell structures of the type including an injector and a plurality of adjacent NPN transistors spaced from said injector, characterized in that at least two PNP transistors have different factors L.sub.B /W.sub.B, where L.sub.B is the base dimension of the NPN transistor opposite the injector, and W.sub.B is the base width of the PNP transistor of the injector.
    Type: Grant
    Filed: July 13, 1978
    Date of Patent: July 7, 1981
    Assignee: International Business Machines Corporation
    Inventors: Robert M. Hornung, Gerard M. Lebesnerais
  • Patent number: 4164668
    Abstract: A method and structure for correcting the voltage coefficient of resistance (VCR) of a resistor in a semiconductor body is described. The resistor may be diffused or ion implanted of one conductivity and formed in an isolated layer of the opposite type of conductivity. The layer is typically an epitaxial layer. A potential V.sub.1 is applied to one end of the resistor and a potential V.sub.2 being applied to the opposite end. The method provides means for controlling variations of the potential difference between the resistive region and the epitaxial layer, either to minimize them or to cause the distortions generated by such variations to be compensated for by equal distortions of opposite directions, such that the overall distortion will be equal to zero. There is provided means to cause the potential of the epitaxial layer to reach a suitable value, preferably a value that varies in the same manner as the average value of the resistor whose VCR is to be corrected.
    Type: Grant
    Filed: May 12, 1977
    Date of Patent: August 14, 1979
    Assignee: International Business Machines Corporation
    Inventors: Francois X. Delaporte, Robert M. Hornung, Anne-Marie Lamouroux, Gerard M. Lebesnerais, Jean-Paul J. Nuez