Abstract: A system for crystallogenesis by diffusion, intended in particular for use on board a space ship, and in which a substance to be crystallized contained in a crucible (18) is brought into contact with a precipitating agent.

Abstract: A PIN photodiode having a low leakage current comprises a substrate (10) of indium phosphide (InP) which is n.sup.+ doped and on whose first surface is formed a layer (11) of indium phosphide (InP) which is n.sup.- doped and on which is disposed a MESA structure formed by a layer (12) of gallium indium arsenide (InGaAs) which is n.sup.- doped and is moreover constituted by a layer (13, 113, 213) of the p.sup.+ type formed at the surface, at the edges and along the circumference of the MESA structure. The structure further comprises a metallic contact (22) formed on the second surface of the substrate and an ohmic contact (21) formed on a part of the p.sup.+ layer. The invention is characterized in that the n.sup.- doping of the layer of indium phosphide (InP) (11) is chosen to be lower than the n.sup.- doping of the layer of gallium indium arsenide (InGaAs) (12), and in that the ohmic contact (21) is formed on a part (213) of the p.sup.

Abstract: This circuit comprising conductive lines for the transfer of high-speed signals is formed from a semiconductor material in the presence of a two-dimensional gas 2DG between two of its layers (3 and 4). By a suitable choice of the conditions of the temperature and of the magnetic field B, it is then made superconducting, thus permitting the transport of high-speed signals without delay and without distortion of the signals.

Abstract: An integrated circuit structure to be built on a semiconductor substrate wafer for the purpose of undertaking a quality check of the wafer has a plurality of field effect transistors laterally disposed in the same close adjacency as transistors which are to be manufactured on a chip using the wafer material. Each field effect transistor has its own well structure, its own source structure, and its own drain structure. The individual field effect transistors have pads allocated thereto at an edge of the structure. Each transistor source/drain structure is connected to the pads by a conductor, the totality of these conductors having width and/or length dimensions so that each run has approximately the same resistance. Only one common gate conductor for all of the transistors is provided.

Abstract: The invention relates to a method of manufacturing field effect transistors of gallium arsenide obtained by ion implantation of light donors, such as silicon or selenium, in a semi-insulating substrate of gallium arsenide. In order to reduce out-diffusion of the deep level (EL.sub.2) responsible for parasitic phenomena in the operation of the transistors, the method is characterized in that in addition oxygen ions are implanted in at least the region of the substrate intended to form the channel region of the field effect transistor. After implantation, the substrate is sintered at a temperature between 600.degree. and 900.degree. C. in either an enveloping substance or uncovered, and/or in an atmosphere of arsine.

Abstract: The invention relates to a method of treating a substrate of gallium arsenide by a double ion implantation. A first implantation of silicon ions (Si.sup.+) is carried out on the entire surface of the substrate, and a second implantation of oxygen ions (O.sup.+) is carried out in regions intended to become isolated regions. A thermal annealing treatment, preferably under encapsulation, follows these ion implantations. These implantations are carried out in order to obtain at the surface of the substrate regions of n-conductivity type isolating regions separated from each other for subsequent manufacture of semiconductor devices. The invention also relates to a gallium arsenide substrate thus treated and to a semiconductor device obtained by the technique of two ion implantations.