Abstract: In the field of large-scale-integrated digital GaAs circuits, a high-entrance high-speed logical operator utilizing so-called "quasi-normally-off" Schottky-gate field-effect transistors (MESFETS) having a low threshold voltage. By means of a single very-high-speed logic gate, the operator thus performs AND - NAND - OR functions by utilizing in an input branch a saturable resistive load in series with a pair of quasi-normally-off MESFET's each having a maximum of two Schottky gates, the drains of the transistors being connected to an output transistor of the same type. Two identical portions of circuit are mounted in parallel with an output half-branch comprising a diode in series with another saturable resistive load.

Abstract: A high-speed logic inverter, in the form of an integrated circuit, with a single supply source, using field-effect transistors of the "quasi-normally-off" type, and the logic operators having several inputs and several outputs which derive therefrom.One embodiment of the invention starts from an inverter with input, through a diode, on a field-effect transistor gate, and with its output at the source of a field-effect transistor. This basic diagram is added to by providing the input (between supply pole and input terminal) with two pairs of diodes ending at the gates of a dual-gate transistor, and by providing independent outputs obtained by connecting the common drain connected transistor gates to the supply pole distinct from ground.

Abstract: Device for regenerating digital signals transmitted along a coaxial line.So as to transmit information at flow rates greater than or equal to 650 Mbauds, the storage comparator of the invention is constructed in the form of an integrated circuit on AsGa and with negative threshold voltage MESFET transistors. It comprises an adjustable threshold voltage comparator stage, a type-D flip-flop for storage and resynchronization with respect to an external clock, and an output matching stage which may provide summation at its output.

Abstract: A method of manufacturing a logic circuit having at least one field effect transistor connected in series with at least one saturable resistor, wherein an active semiconductor layer is formed with a predetermined thickness on a semi-insulating substrate, ohmic contacts are deposited to produce source and drain regions for the resistor and the transistor, a Schottky contact is deposited between the resistor source and drain ohmic contacts to form a gate region which is then electrically connected to the resistor source contact by means of a metal connection, whereupon the localized thickness of the active layer is measured by measuring the drain-source current to the resistor upon application of a predetermined voltage thereto and a groove then cut between the source and drain contacts of the field effect transistor to obtain a predetermined channel depth from the bottom of the groove to the semi-insulating substrate.

Abstract: A logic circuit including an input stage, wherein a first field-effect transistor is in series with a first saturable resistor interposed on the drain side in the supply of the first transistor, and an output stage including a second transistor which is identical with the first and has a supply on the drain side which is common with the input stage supply. The gate of the second transistor is connected to the drain of the first transistor. The supply circuit of the second transistor is closed across a forward-biased diode, and a second saturable resistor on the ground of the common supply is connected to the source of the first transistor. At least a selected of the field effect transistors or the saturable resistors has a saturable resistor structure formed of a layer of semiconductor material on a semi-insulating substrate. The material is doped to set up a dipolar domain in respect of an electric field which is higher than a so-called critical value.

Abstract: A structure for logic circuits comprises a current source formed by a PNP transistor and two complementary transistors integrated on the same N-type substrate. A buried plate and P-type walls forms insulating housings. These two complementary transistors are of the vertical type and the PNP transistor has the buried layer as its collector. This buried layer and the insulating walls enable current to be injected into the PNPN structure which eliminates the need for surface interconnection networks and increases the integration density.

Abstract: An integrated circuit and process for producing an integrated circuit. The circuit includes two interconnection layers, a lower layer being separated from the substrate by a thin dielectric layer, and separated from the upper layer by a thick dielectric layer, the interconnections between the two interconnection layers being situated outside the zone of the active elements of the integrated circuit. The circuit comprises active elements deposited for example on portions of an n-type layer supported by a substrate of semi-insulating gallium arsenide. Ohmic and Schottky contacts are connected either to the lower interconnection layer or to the upper interconnection layer. The thin dielectric layer is for example a silica layer whose thickness is less than 1,000 Angstroms, the thick dielectric layer having a thickness of 5,000 to 10,000 Angstroms.

Abstract: A method of adjusting the threshold voltages of field effect transistors, in particular of SCHOTTKY gate field-effect transistors, is provided. During the process of manufacture of the transistor, the channel charge carrier density is modified by ion implantation. A monitoring device, in the form of a test transistor, is manufactured at the same time as the production transistors and on the same wafer thereas. An appendix of the test transistor makes it possible to measure the threshold voltage and saturation current, during ionic implantation.