Patents by Inventor Gerard Passemard

Gerard Passemard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Horizontal nanotube/nanofiber growth method
    Patent number: 8114777
    Abstract: A method for forming a nanotube/nanofiber growth catalyst on the sides of portions of a layer of a first material, comprising the steps of depositing a thin layer of a second material; opening this layer at given locations; depositing a very thin catalyst layer; depositing a layer of the first material over a thickness greater than that of the layer of the second material; eliminating by chem./mech. polishing the upper portion of the structure up to the high level of the layer of the second material; and eliminating the second material facing selected sides of the layer portions of the first material.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: February 14, 2012
    Assignees: STMicroelectronics, Commissariat a l'energie Atomique
    Inventors: Gérard Passemard, Sylvain Maitrejean, Valentina Ivanova-Hristova
  • Horizontal nanotube/nanofiber growth method
    Publication number: 20090212006
    Abstract: A method for forming a nanotube/nanofiber growth catalyst on the sides of portions of a layer of a first material, comprising the steps of depositing a thin layer of a second material; opening this layer at given locations; depositing a very thin catalyst layer; depositing a layer of the first material over a thickness greater than that of the layer of the second material; eliminating by chem./mech. polishing the upper portion of the structure up to the high level of the layer of the second material; and eliminating the second material facing selected sides of the layer portions of the first material.
    Type: Application
    Filed: December 19, 2008
    Publication date: August 27, 2009
    Inventors: Gerard Passemard, Sylvain Maitrejean, Valentina Ivanova-Hristova
  • Process for fabricating interconnect networks
    Patent number: 7064061
    Abstract: The process includes depositing a filling material in trenches formed in at least one layer of dielectric so as to fill open pores in the dielectric. The filling material is intended to prevent the subsequent diffusion of the interconnect metal and/or of a metal of a diffusion barrier, and may be non-porous. The filling material preferably has a low dielectric constant.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: June 20, 2006
    Assignees: STMicroelectronics SA, Commissariat a l'Energie Atomique
    Inventors: Gérard Passemard, Emmanuel Sicurani, Charles Lecornec
  • Method for making interconnection networks
    Publication number: 20040115910
    Abstract: The process includes depositing a filling material in trenches formed in at least one layer of dielectric so as to fill open pores in the dielectric. The filling material is intended to prevent the subsequent diffusion of the interconnect metal and/or of a metal of a diffusion barrier, and may be non-porous. The filling material preferably has a low dielectric constant.
    Type: Application
    Filed: November 24, 2003
    Publication date: June 17, 2004
    Inventors: Gerard Passemard, Emmanuel Sicurani, Charles Lecornec
  • Damascene-type interconnection structure and its production process
    Patent number: 6624053
    Abstract: A interconnection structure of the damascene type is produced on a surface of a microelectronic device that includes at least one dielectric material layer for housing at least one interconnection and at least one interface layer on the dielectric material layer. The interface layer may include at least one SiCH layer and at least one SiOCH layer.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: September 23, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Gérard Passemard
  • Damascene-type interconnection structure and its production process
    Publication number: 20010004550
    Abstract: A interconnection structure of the damascene type is produced on a surface of a microelectronic device that includes at least one dielectric material layer for housing at least one interconnection and at least one interface layer on the dielectric material layer. The interface layer may include at least one SiCH layer and at least one SiOCH layer.
    Type: Application
    Filed: December 6, 2000
    Publication date: June 21, 2001
    Applicant: STMicroelectronics S.A.
    Inventor: Gerard Passemard