Abstract: A multi-way set associative cache memory 6 is provided with lockdown control circuitry 26, 48 for controlling portions of that cache memory to store data which is locked within the cache memory 6 (i.e. not subject to eviction). Programmable lockdown data 38, 40, 42, 44, 46 specifies which ways contain any locked portions and also the size within each way of locked portion. Thus, individual cache ways can be partially locked.

Abstract: The present invention provides a data processing apparatus and method for testing power management instructions. The data processing apparatus comprises a processor for executing data processing instructions including power management instructions, at least one of the power management instructions being a command power management instruction. A power management controller is also provided for receiving command data from the processor when a command power management instruction is executed by the processor, and to control power management logic to perform an associated set of power management functions dependent on the command data. The data processing apparatus includes first power management logic controllable by the power management controller, with the power management controller also having an interface to enable communication with additional power management logic.

Abstract: A data processing system includes a processor core, a cache memory and a cache controller which operate to allow data accesses to a cache line for which a pending cache linefill operation exists to be serviced for those data words within the cache line that are valid at a particular point in time. One or more status bits are provided in association with each cache line indicating whether a line fill is pending for that cache line. The old data may be manipulated up to the point where the first new data is returned. New data items may be read once they have been written into a victim cache line even though the cache linefill is not completed. Stores to the victim cache line may be made via a fill buffer even though the linefill is still pending. The cache memory may include a content addressable memory (CAM) and the cache memory and controller may support a hit under miss operation.

Abstract: The present invention relates to a memory device and method for reducing leakage current during a power down mode of operation. The memory device comprises a column of memory cells, with each memory cell being arranged to store a data value, and a pair of bit lines coupled to the column of memory cells. Bit line precharge circuitry is provided for precharging the pair of bit lines to a predetermined voltage level during a precharge phase, the pair of bit lines being arranged such that, when a particular memory cell in the column is selected in an evaluate phase following the precharge phase, a relative change in voltage level between the pair of bit lines indicates the data value stored within the selected memory cell.