Abstract: An electrically-programmable integrated circuit memory in which the selected memory cell is read by comparing its current output with that of a reference cell, plus a bias current. The bias current is different in test mode than it would be during a normal read operation. The result of this is that, in test mode, cells whose current output is marginal in the unprogrammed state will be detected as faulty, even though those same cells would correctly be read as unprogrammed.

Abstract: A device for neutralizing the access to an integrated-circuit zone to be protected. A fuse section providing a connection between an access terminal and an integrated circuit zone to be protected is connected by means of the fuse end portion located nearest the zone to be protected to a junction obtained at the intersection of a layer of a conductivity type opposite to the conductivity type in which the substrate of the integrated circuit is formed. This junction is reverse-biased during normal utilization of the circuit and forward-biased only when it is desired to melt the fuse, thus making the zone to be protected irreversibly inaccessible.

Abstract: A voltage switch-over circuit, depending on a switch-over signal, delivers either a first voltage Vpp or a second voltage Vcc at its output, the voltage Vpp being greater than the voltage Vcc. The said circuit consists of a first MOS transistor with one of its electrodes connected to the voltage Vcc and a set of two series-connected MOS transistors with one of their electrodes connected to the voltage Vpp and with their two gates connected together so as to create a floating node at the common point between the two MOS transistors, the other electrode of the first MOS transistor and the other electrode of the set of two MOS transistors being connected together, and the gates of the first MOS transistor and those of the set of two MOS transistors respectively receiving the switch-over signal and the reverse switch-over signal.

Abstract: A safety device for an electrically programmable read-only memory of the type comprising a matrix of memory cells, each comprising a floating gate MOS transistor that exhibits a defined threshold voltage after programming, each cell being accessible by rows and columns connected to means which can be used to apply, to these rows and columns, potentials representing the data to be recorded in the cells or potentials representing the command for reading the recorded data. This device comprises at least one reference memory cell included in the memory, the memory cell exhibiting a threshold voltage, after programming, which is lower than the minimum of the dispersal of threshold voltages of the transistors of the matrix.