Abstract: Methods, systems and computer program products for loading, storing and executing dynamically modifiable functional exercisers are provided. Aspects also include receiving a plurality of functional exercisers by a secondary reload memory disposed on a device-under-test. Aspects include loading at least a first functional exerciser from the secondary reload memory into a primary execution memory disposed on the device-under-test. Aspects include executing and modifying the first functional exerciser stored in the primary execution memory. Aspects further include, responsive to determining based on a test algorithm that one or more functional exercisers of the plurality have not been fully executed, loading a second functional exerciser from the secondary reload memory into the primary execution memory.

Abstract: Methods, systems and computer program products for loading, storing and executing dynamically modifiable functional exercisers are provided. Aspects also include receiving a plurality of functional exercisers by a secondary reload memory disposed on a device-under-test. Aspects include loading at least a first functional exerciser from the secondary reload memory into a primary execution memory disposed on the device-under-test. Aspects include executing and modifying the first functional exerciser stored in the primary execution memory. Aspects further include, responsive to determining based on a test algorithm that one or more functional exercisers of the plurality have not been fully executed, loading a second functional exerciser from the secondary reload memory into the primary execution memory.

Abstract: A method for performing static timing analysis on digital electronic circuits is disclosed. A snip (or DC adjust) file is initially generated. Static timing analysis is then performed on the final circuit netlist using the snip file. If the final circuit netlist meets all the timing constraints, the snip file is converted to a group of cutpoints, and formal verification is performed on the cutpoints. A determination is made as to whether or not the cutpoints pass formal verification. If the cutpoints pass formal verification, the user analysis on the final circuit netlist is completed, and the final circuit netlist can proceed to manufacturing. Otherwise, if the cutpoints do not pass formal verification, a flag is issued to alert a user. The user then has to either modify certain snip point(s) within the snip file or modify the circuit netlist, and perform the user analysis again.

Abstract: A method and circuit for adjusting the read margin of a self-timed memory array. The electronic circuit, including: a memory cell array including a sense amplifier self-timed decode circuit adapted to set a base read time delay of the memory cell array; and a read delay adjustment circuit coupled to the memory cell array, the read delay adjustment circuit adapted to adjust the base read time delay of the memory array based on an operating frequency of the memory cell array.

Abstract: A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.

Abstract: A method and apparatus for providing a more accurate reading of the junction temperature within an Integrated Circuit (IC) where temperature sensing elements are used that are sensitive to process changes. The apparatus stores an offset value in the IC that is used by internal temperature reading circuitry to adjust the temperature read/calculated from the sensing elements to more accurately reflect the actual junction temperature.