Patents by Inventor Gerard T. Quilligan
Gerard T. Quilligan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11522552Abstract: An analog digital converter that does not require a dedicated reference voltage, can digitize a rail-rail input signal and provide house-keeping functions to a ROIC or other IC. The RHADR system may operate without support from a main electronics board, which would only have to supply a power supply voltage to, and read the outputs from, the chip. This is achieved with (1) a Pivoting Successive Approximation Register ADC (PSAR ADC) and (2) radiation hard by design (RHBD) techniques.Type: GrantFiled: July 13, 2021Date of Patent: December 6, 2022Assignee: United States of America as represented by the Administrator of NASAInventors: Gerard T. Quilligan, Shahid Aslam, Terry A. Hurford
-
Patent number: 11496133Abstract: Embodiments may provide a radiation hardened low-power data acquisition system-on-chip (SOC) suitable for space flight. The various embodiments may provide the radiation hardened low-power data acquisition SOC having a radiation hardened semiconductor die, a radiation hardened multiplexer integrated on the radiation hardened semiconductor die and configured to receive a plurality of analog signals and selectively output an analog signal of the plurality of analog signals, at least one radiation hardened analog to digital converted integrated on the radiation hardened semiconductor die and configured to convert the analog signal to a digital signal, and a radiation hardened serial communication interface integrated on the radiation hardened semiconductor die and configured to output the digital signal.Type: GrantFiled: July 29, 2021Date of Patent: November 8, 2022Assignee: United States of America as represented by the Administrator of NASAInventors: George Suarez, Jeffrey J. DuMonthier, Gerard T. Quilligan
-
Patent number: 11476804Abstract: A clock source includes a comparator having a positive comparator input, a negative comparator input, a proportional to absolute temperature (PTAT) PMOS bias input, a PTAT NMOS bias input, and a comparator output, a resonator element, series and feedback resistors and other passive components coupled between the comparator output and the negative comparator input to generate a signal with approximately constant gain and frequency at the comparator output, and a PTAT bias circuit coupled to the comparator's PTAT PMOS and NMOS bias inputs, and configured to drive the PTAT PMOS bias input and the PTAT NMOS bias input to maintain approximately constant gain and frequency over the operating temperature range of the clock source.Type: GrantFiled: November 22, 2021Date of Patent: October 18, 2022Assignee: United States of America as represented by the Administrator of NASAInventors: Gerard T. Quilligan, Terry Hurford
-
Patent number: 11391672Abstract: An apparatus for measuring vapor partial pressures of water and carbon dioxide includes a pair of infrared (IR) sources and a pair of quad filter detectors are placed opposite to one another such that the vapor partial pressures of water (H2O) and carbon dioxide (CO2) is measured and quantified in a short pathlength gas cell.Type: GrantFiled: August 25, 2020Date of Patent: July 19, 2022Assignee: United States of America as represented by the Administrator of NASAInventors: Shahid Aslam, Daniel P. Glavin, Gerard T. Quilligan, Nicolas Gorius, Perry A. Gerakines, John R. Kolasinski, Dat Tran, Todd C. Purser
-
Patent number: 10158335Abstract: A Gated CDS Integrator (GCI) may amplify low-level signals without introducing excessive offset and noise. The GCI may also amplify the low level signals with accurate and variable gain. The GCI may include a modulator preceding an amplifier such that offset or noise present in a signal path between the modulator and a demodulator input is translated to a higher out of band frequency, and thereafter reduced by a double sampled discrete time integrator which also reduces thermal noise. The thermal noise may also be reduced by averaging the output of the discrete time integrator.Type: GrantFiled: September 27, 2016Date of Patent: December 18, 2018Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Gerard T. Quilligan, Shahid Aslam
-
Patent number: 9985594Abstract: A Gated CDS Integrator (GCI) may amplify low-level signals without introducing excessive offset and noise. The GCI may also amplify the low level signals with accurate and variable gain. The GCI may include a modulator preceding a linear amplifier such that offset or noise present in a signal path between the modulator and a demodulator input is translated to a higher out of band frequency.Type: GrantFiled: September 8, 2015Date of Patent: May 29, 2018Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Gerard T. Quilligan, Shahid Aslam
-
Patent number: 9685913Abstract: An autozero amplifier may include a window comparator network to monitor an output offset of a differential amplifier. The autozero amplifier may also include an integrator to receive a signal from a latched window comparator network, and send an adjustment signal back to the differential amplifier to reduce an offset of the differential amplifier.Type: GrantFiled: September 10, 2015Date of Patent: June 20, 2017Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Gerard T. Quilligan, Shahid Aslam
-
Publication number: 20170077876Abstract: An autozero amplifier may include a window comparator network to monitor an output offset of a differential amplifier. The autozero amplifier may also include an integrator to receive a signal from a latched window comparator network, and send an adjustment signal back to the differential amplifier to reduce an offset of the differential amplifier.Type: ApplicationFiled: September 10, 2015Publication date: March 16, 2017Inventors: GERARD T. QUILLIGAN, SHAHID ASLAM
-
Publication number: 20170019080Abstract: A Gated CDS Integrator (GCI) may amplify low-level signals without introducing excessive offset and noise. The GCI may also amplify the low level signals with accurate and variable gain. The GCI may include a modulator preceding an amplifier such that offset or noise present in a signal path between the modulator and a demodulator input is translated to a higher out of band frequency, and thereafter reduced by a double sampled discrete time integrator which also reduces thermal noise. The thermal noise may also be reduced by averaging the output of the discrete time integrator.Type: ApplicationFiled: September 27, 2016Publication date: January 19, 2017Inventors: Gerard T. Quilligan, Shahid Aslam
-
Publication number: 20160294332Abstract: A Gated CDS Integrator (GCI) may amplify low-level signals without introducing excessive offset and noise. The GCI may also amplify the low level signals with accurate and variable gain. The GCI may include a modulator preceding a linear amplifier such that offset or noise present in a signal path between the modulator and a demodulator input is translated to a higher out of band frequency.Type: ApplicationFiled: September 8, 2015Publication date: October 6, 2016Inventors: Gerard T. Quilligan, Shahid Aslam
-
Publication number: 20120069321Abstract: An apparatus and method for imaging a target area is provided. Light is directed to a target area where it reflects off objects. The light is then returned to a receiving device. This receiving device creates a signal indicative of the intensity of the received light. The time of flight for the light plus the shape of the signal are analyzed to determine the range and shape of objects in the target area.Type: ApplicationFiled: September 22, 2010Publication date: March 22, 2012Inventors: Gerard T. Quilligan, Jeffrey J. DuMonthier, George Suarez
-
Patent number: 7426372Abstract: An apparatus and method for amplifying a radio frequency signal including, generating a plurality of shaped pulses utilizing a piecewise linearizer circuit, applying the plurality of shaped pulses to a first input of a radio frequency amplifier circuit, and injecting a radio frequency carrier into a second input of the radio frequency amplifier circuit. The apparatus comprises a piecewise linearizer (PWL) circuit coupled to the input of a Radio Frequency Digital to Analog Converter (RFDAC) operating as a signal amplifier.Type: GrantFiled: March 31, 2005Date of Patent: September 16, 2008Assignee: M/A-COM Eurotec B.V.Inventor: Gerard T. Quilligan
-
Patent number: 7183958Abstract: An apparatus and method for amplifying a radiofrequency signal using a main Digital to Analog Converter (RFDAC) and a subordinate Digital to Analog Converter (Sub-DAC). The main RFDAC provides a first portion of a N-bit digital output, which specifies the amplification level of the radiofrequency signal, and the sub-DAC provides a second portion of the N-bit digital word. Together, the main RFDAC and the Sub-DAC convert a complete N-bit digital word, where N specifies the resolution of the output radiofrequency signal.Type: GrantFiled: September 8, 2004Date of Patent: February 27, 2007Assignee: M/A-Com, Eurotec B.V.Inventors: Gerard T. Quilligan, Pierce J. Nagle, Eugene P. Heaney