Abstract: Techniques are disclosed relating to an I/O agent circuit of a computer system. The I/O agent circuit may receive, from a peripheral component, a set of transaction requests to perform a set of read transactions that are directed to one or more of a plurality of cache lines. The I/O agent circuit may issue, to a first memory controller circuit configured to manage access to a first one of the plurality of cache lines, a request for exclusive read ownership of the first cache line such that data of the first cache line is not cached outside of the memory and the I/O agent circuit in a valid state. The I/O agent circuit may receive exclusive read ownership of the first cache line, including receiving the data of the first cache line. The I/O agent circuit may then perform the set of read transactions with respect to the data.

Abstract: Techniques are disclosed relating to an I/O agent circuit of a computer system. The I/O agent circuit may receive, from a peripheral component, a set of transaction requests to perform a set of read transactions that are directed to one or more of a plurality of cache lines. The I/O agent circuit may issue, to a first memory controller circuit configured to manage access to a first one of the plurality of cache lines, a request for exclusive read ownership of the first cache line such that data of the first cache line is not cached outside of the memory and the I/O agent circuit in a valid state. The I/O agent circuit may receive exclusive read ownership of the first cache line, including receiving the data of the first cache line. The I/O agent circuit may then perform the set of read transactions with respect to the data.

Abstract: The present invention relates to a smart wallet that is comprised of a plurality of security features such as a voice-activated magnetic lock and a bio-metric fingerprint, wherein each lock may be programmed via a mobile application. The smart wallet is further comprised of a camera that allows a user to view the surroundings of the wallet if lost or a criminal who may have stolen the wallet, and an internal battery that may power the camera and lock and may also serve as a personal and portable power bank that allows a user to charge their personal belongings via a plurality of USB-Ports. The smart wallet also includes an RFID shield, and a user may create virtual versions of any card type within the wallet, wherein the user may then pair the mobile application with the wallet to use the app to pay for goods/services.

Abstract: A method for providing memory protection within a signal processing system comprises receiving a memory access signal comprising at least one instruction memory region (IMR) indication. The IMR indication comprises an indication of a region of memory from which a memory access instruction was fetched, execution of said memory access instruction having resulted in the generation of the received memory access signal. The method further comprises comparing the IMR indication for the received memory access signal to at least one permitted memory region (PMR) indication for a target address of the received memory access signal, and determining whether a memory access being attempted by the memory access signal is permitted based at least partly on the comparison of the IMR indication for the received memory access signal to the PMR indication for the target address of the received memory access signal.

Abstract: A method for providing memory protection within a signal processing system comprises receiving a memory access signal comprising at least one instruction memory region (IMR) indication. The IMR indication comprises an indication of a region of memory from which a memory access instruction was fetched, execution of said memory access instruction having resulted in the generation of the received memory access signal. The method further comprises comparing the IMR indication for the received memory access signal to at least one permitted memory region (PMR) indication for a target address of the received memory access signal, and determining whether a memory access being attempted by the memory access signal is permitted based at least partly on the comparison of the IMR indication for the received memory access signal to the PMR indication for the target address of the received memory access signal.

Abstract: Embodiments of the present disclosure provide new systems and methods for e-commerce, or online product and service sales. These systems and methods allow for a vendor to list a product on which buyers can place puts. Vendors can then evaluate the puts, learning valuation information about their listed item, and respond to the puts with an offer or rejection. The buyers may then redeem offers at a merchant using a physical or virtual coupon.

Abstract: The present invention provides a nuclear activation apparatus for one or more fluid samples comprising the following modules; a means for introducing one or more fluid samples to a sample conduit, an activation thimble, comprising a section of sample conduit configured for multiple passes adjacent a radiation source, an absorber located adjacent to the activation thimble, and a detector located adjacent the sample conduit, wherein the relative arrangement of the modules can be altered specific to an application and the rate of flow of the fluid sample adjacent the radiation source can be controlled.

Abstract: A control system for transferring a sample from a source vessel to a target vessel generally includes a vessel unit, a primary transfer unit, an x-drive, a y-drive, a z-drive and a control unit for controlling the drives. The vessel unit includes a support plate for supporting the source vessel and the target vessel thereon and the transfer unit includes at least one transfer device for transferring the sample from the source vessel to the target vessel. The x-, y- and z-drives reciprocally translate one of the support plate and the transfer device in a respective x-direction, y-direction and z-direction, wherein the x, y and z directions define a three axis Cartesian coordinate system.

Abstract: The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache comprising a plurality of storage locations and said data processor comprising a cache directory operable to store a physical address indicator for each storage location comprising stored data; a hash value generator operable to generate a generated hash value from at least some of said bits of said address said generated hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to said plurality of storage locations within said cache; wherein in response to a request to access said data item said data processor is operable to compare said generated hash value with at least some of said plurality of hash values stored within said buffer and in response to a match to indicate a indicated storage location of said data item; and said data processor is operable to access

Abstract: A control system for transferring a sample from a source vessel to a target vessel generally includes a vessel unit, a primary transfer unit, an x-drive, a y-drive, a z-drive and a control unit for controlling the drives. The vessel unit includes a support plate for supporting the source vessel and the target vessel thereon and the transfer unit includes at least one transfer device for transferring the sample from the source vessel to the target vessel. The x-, y- and z-drives reciprocally translate one of the support plate and the transfer device in a respective x-direction, y-direction and z-direction, wherein the x, y and z directions define a three axis Cartesian coordinate system.

Abstract: A transfer unit for transferring a sample from a source vessel to a target vessel. The transfer unit includes a transfer device having a pin tip with a central bore terminating at a bottom wall, an actuating element movably disposed in the pin tip bore, an actuator rod for moving the actuating element and a compensating device connected between the actuating element and the actuator rod. The actuator rod moves the actuating element between a first position adjacent the tip bottom wall and a second position away from the bottom wall. Movement of the actuating element causes a sample in proximity to the pin tip to be alternately collected and released from the pin tip. Such movement also defines a stroke length for the actuator rod, wherein the compensating device compensates for any variations in the actuator rod stroke length. The transfer unit further includes a tip ejector for removing the disposable tips from the transfer device and a tip loading station for applying the tips to the transfer device.

Abstract: A system and method for facilitating integrated mine planning in a mining operation. The system has a data module to store data objects. The system also has a management module in communication with the data module and the management module is configured with at least one workflow having a series of interdependent processing steps representative of planning steps for a mine plan. The management module controls the accessibility of one or more users to each of the steps within the at least one workflow. The at least one user is able to obtain one or more data objects from the data store, under the control of the management module, to process the one or more data objects to perform at least one processing step in the at least one workflow using a proprietary expert software solution.

Abstract: A control system for transferring a sample from a source vessel to a target vessel generally includes a vessel unit, a primary transfer unit, an x-drive, a y-drive, a z-drive and a control unit for controlling the drives. The vessel unit includes a support plate for supporting the source vessel and the target vessel thereon and the transfer unit includes at least one transfer device for transferring the sample from the source vessel to the target vessel. The x-, y- and z-drives reciprocally translate one of the support plate and the transfer device in a respective x-direction, y-direction and z-direction, wherein the x, y and z directions define a three axis Cartesian coordinate system.

Abstract: A pegboard assembly is secured in a spaced relation against a wall. The pegboard assembly has a plurality of pegboard members, in which a first pegboard member is coupled to a second pegboard member by a connector. The pegboard member has a front side and a rear side, and has a plurality of holes defined therethrough. The rear side has an integral spacer element and is adapted to contact the wall such that the holes are adapted to be spaced from the wall.

Abstract: A pegboard assembly is secured in a spaced relation against a wall. The pegboard assembly has a plurality of pegboard members, in which a first pegboard member is coupled to a second pegboard member by a connector. The pegboard member has a front side and a rear side, and has a plurality of holes defined therethrough. The rear side has an integral spacer element and is adapted to contact the wall such that the holes are adapted to be spaced from the wall.

Abstract: A pegboard assembly is secured in a spaced relation against a wall. The pegboard assembly has a plurality of pegboard members, in which a first pegboard member is coupled to a second pegboard member by a connector. The pegboard member has a front side and a rear side, and has a plurality of holes defined therethrough. The rear side has an integral spacer element and is adapted to contact the wall such that the holes are adapted to be spaced from the wall.

Abstract: The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache comprising a plurality of storage locations and said data processor comprising a cache directory operable to store a physical address indicator for each storage location comprising stored data; a hash value generator operable to generate a generated hash value from at least some of said bits of said address said generated hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to said plurality of storage locations within said cache; wherein in response to a request to access said data item said data processor is operable to compare said generated hash value with at least some of said plurality of hash values stored within said buffer and in response to a match to indicate a indicated storage location of said data item; and said data processor is operable to access

Abstract: The application discloses a data processor operable to process data, said data processor comprising: a cache having a data item storage location identified by an address; a hash value generator operable to generate a hash value from at least some of said bits of said address said hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to a plurality of storage locations within said cache; wherein in response to a request to access said data item storage location said data processor is operable to compare a hash value generated from said address with at least some of said plurality of hash values stored within said buffer. The comparison providing an indication of the storage location of the data item.

Abstract: A data processor operable to process data said data processor being operable to perform a plurality of processes or a plurality of applications on said data, said data processor comprising: a cache; a data storage unit operable to store a process or application identifier defining a process or application that is currently executing on said data processor on said data; wherein a data item storage location within said cache is indicated by an address, and said data processor further comprises: a hash value generator operable to generate a hash value from at least some of said bits of said address and at least some bits of said process or application identifier, said hash value having fewer bits than said address.