Abstract: A magnetoresistive memory cell includes a magnetoresistive layer stack containing a reference layer, a nonmagnetic spacer layer, and a free layer. A ferroelectric material layer having two stable ferroelectric states is coupled to a strain-modulated ferromagnetic layer to alter a sign of magnetic exchange coupling between the strain-modulated ferromagnetic layer and the free layer. The strain-modulated ferromagnetic layer may be the reference layer or a perpendicular magnetic anisotropy layer that is located proximate to the ferroelectric material layer. The magnetoresistive memory cell may be configured as a three-terminal device or as a two-terminal device, and may be configured as a tunneling magnetoresistance (TMR) device or as a giant magnetoresistance (GMR) device.

Abstract: A magnetoresistive memory cell includes a magnetoresistive layer stack containing a reference layer, a nonmagnetic spacer layer, and a free layer. A ferroelectric material layer having two stable ferroelectric states is coupled to a strain-modulated ferromagnetic layer to alter a sign of magnetic exchange coupling between the strain-modulated ferromagnetic layer and the free layer. The strain-modulated ferromagnetic layer may be the reference layer or a perpendicular magnetic anisotropy layer that is located proximate to the ferroelectric material layer. The magnetoresistive memory cell may be configured as a three-terminal device or as a two-terminal device, and may be configured as a tunneling magnetoresistance (TMR) device or as a giant magnetoresistance (GMR) device.

Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.

Abstract: A two-step SET pulse may be applied to a phase change material of a phase change memory cell in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

Abstract: A phase change memory device includes a phase change material portion located between a first electrode and a second electrode, and a crystallization template material portion located between the first electrode and the second electrode in contact with the phase change material portion. The crystallization template material portion and the phase change material portion belong to a same crystal system and have matching lattice spacing, or the crystallization template material portion and the phase change material portion do not belong to the same crystal system, but have a matching translational symmetry along at least one paired lattice plane with a matching lattice spacing.

Abstract: A phase change memory device includes a phase change material portion located between a first electrode and a second electrode, and a crystallization template material portion located between the first electrode and the second electrode in contact with the phase change material portion. The crystallization template material portion and the phase change material portion belong to a same crystal system and have matching lattice spacing, or the crystallization template material portion and the phase change material portion do not belong to the same crystal system, but have a matching translational symmetry along at least one paired lattice plane with a matching lattice spacing.

Abstract: Systems and methods for improving the crystallization of a phase change material of a phase change memory cell are described. A two-step SET pulse may be applied to the phase change material in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

Abstract: Systems and methods for improving the crystallization of a phase change material of a phase change memory cell are described. A two-step SET pulse may be applied to the phase change material in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

Abstract: Systems and methods for improving the crystallization of a phase change material of a phase change memory cell are described. A two-step SET pulse may be applied to the phase change material in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.

Abstract: A magnetoresistive memory device includes a magnetic-exchange-coupled layer stack containing a free layer, a reference layer and an electrically conductive, non-magnetic interlayer exchange coupling layer located between the free layer and the reference layer, and an insulating spacer layer located in a series connection with the magnetic-exchange-coupled layer stack between a first electrode and a second electrode. The first electrode and the second electrode are configured to provide a programming voltage across the magnetic-exchange-coupled layer stack and the insulating spacer layer.

Abstract: A magnetoresistive memory device includes a magnetic-exchange-coupled layer stack containing a free layer, a reference layer and an electrically conductive, non-magnetic interlayer exchange coupling layer located between the free layer and the reference layer, and an insulating spacer layer located in a series connection with the magnetic-exchange-coupled layer stack between a first electrode and a second electrode. The first electrode and the second electrode are configured to provide a programming voltage across the magnetic-exchange-coupled layer stack and the insulating spacer layer.

Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.

Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.

Abstract: A magnetic read apparatus includes a read sensor, a shield structure and a side magnetic bias structure. The read sensor includes a free layer having a side and a nonmagnetic spacer layer. The shield structure includes a shield pinning structure and a shield reference structure. The nonmagnetic spacer layer is between the shield reference structure and the free layer. The shield reference structure is between the shield pinning structure and the nonmagnetic spacer layer. The shield pinning structure includes a pinned magnetic moment in a first direction. The shield reference structure includes a shield reference structure magnetic moment weakly coupled with the pinned magnetic moment. The side magnetic bias structure is adjacent to the side of the free layer.

Abstract: A heat assisted magnetic recording (HAMR) media structure is disclosed. The HAMR media structure includes a magnetic recording layer comprising an array of magnetic grains for storing information; a heat sink layer disposed below the magnetic recording layer and having a first thermal conductivity; and an anisotropic thermal barrier layer disposed between the magnetic recording layer and the heat sink layer and having a vertical thermal conductivity and an in-plane thermal conductivity, wherein the vertical thermal conductivity is substantially higher than the in-plane thermal conductivity.

Abstract: A magnetic read apparatus includes a media-facing surface (MFS), a sensor, a shield structure, a side bias structure, and a shield reference bias structure. The sensor includes a free layer and a nonmagnetic layer. The shield structure includes a shield pinning structure and a shield reference structure between the shield pinning structure and the nonmagnetic layer. The nonmagnetic layer is between the free layer and a shield reference structure. The shield pinning structure includes a pinned moment oriented in a first direction. The shield reference structure includes a reference structure moment weakly coupled with the pinned moment. The side bias structure is adjacent to a side of the free layer and biases the free layer in a first direction parallel to the MFS. The shield reference bias structure is adjacent to the shield reference structure and biases the shield reference structure in a direction opposite to the first direction.

Abstract: A recording medium having improved signal-to-noise ratio (SNR) capabilities includes dual cap layers over the recording layer, where the Curie temperature of the first cap layer over the recording layer is greater than the Curie temperature of the recording layer, and the Curie temperature of the second cap layer over the first cap layer is greater than the Curie temperature of the first cap layer. The first cap layer may be composed of a magnetically hard material, such as L10 CoPt, where the second cap layer may be composed of a magnetically soft material, such as Co. Such a medium is particularly useful in the context of heat-assisted magnetic recording (HAMR).

Abstract: A tunnel magnetoresistance (TMR) read sensor having a tabbed AFM layer and an extended pinned layer and methods for making the same are provided. The TMR read sensor has an AFM layer recessed from the air bearing surface, providing a reduced shield-to-shield distance.

Abstract: A soft underlayer (SUL) and methods for making an SUL are provided, the SUL having characteristics that make it compatible with the high temperature requirements associated with heat-assisted magnetic recording (HAMR) media growth and writing, e.g., temperatures greater than 500° C. The SUL may have a high crystallization temperature of greater than 450° C. and a high Curie temperature greater than 300° C., for example. Additionally, the SUL can maintain a saturation magnetization value greater than, e.g., 9 kGauss, at such high temperatures, thereby having the ability to remain amorphous at temperatures up to, e.g., 650° C., and exhibiting a relatively flat integrated noise profile from approximately 300° C. to 650° C. Further still, a spacer layer material is chosen such that inter-diffusion does not occur at these high temperatures.