Abstract: There is provided a method for manufacturing a second semiconductor item, the method comprising: (a) obtaining a first semiconductor item that includes (i) a first mask that comprises first apertures of a first width, (ii) a main dielectric layer that has a first PER, (iii) a VEBCD layer located below the main dielectric layer, the VEBCD layer exhibits a second PER that exceeds the first PER, and (iv) an additional metal layer located below the VEBCD layer that comprises additional metal conductors; (b) forming intermediate holes in the main dielectric layer at locations allocated to vias holes, the intermediate holes have a second width that is smaller than the first width and do not reach the VEBCD layer; and (c) concurrently forming the via holes and line holes to provide the second semiconductor item by applying an etching process while utilizing the VEBCD layer to prevent a width of bottoms of the via holes from exceeding a width of the additional metal conductors.