Abstract: A device includes signal processing circuits, a RAM, and RAM management circuitry. The signal processing circuits produce output data signals as a function of current and past values of sensor data signals. The RAM is organized into a set of RAM sections storing sensor data signal values. The RAM management circuitry has a buffer accessible by the plurality of signal processing circuits, and manages storage and retrieval of data in the RAM sections independently of one another by executing sets of memory operations. A set of memory operations includes a read operation, during which past values of sensor data signals are read from a section of the RAM and stored in the buffer, and a write operation, during which current values of sensor data signals are written into the section of the RAM read during the read operation.

Abstract: A method to arm an airbag, the method including determining, by a system device, that an arming condition for the airbag has been met; delivering a communication to a master device from the system device to inform the master device that the arming condition has been met; snooping the communication by an expansion device; and arming the airbag by the expansion device in response to snooping the arming condition.

Abstract: A device includes signal processing circuits, a RAM, and RAM management circuitry. The signal processing circuits produce output data signals as a function of current and past values of sensor data signals. The RAM is organized into a set of RAM sections storing sensor data signal values. The RAM management circuitry has a buffer accessible by the plurality of signal processing circuits, and manages storage and retrieval of data in the RAM sections independently of one another by executing sets of memory operations. A set of memory operations includes a read operation, during which past values of sensor data signals are read from a section of the RAM and stored in the buffer, and a write operation, during which current values of sensor data signals are written into the section of the RAM read during the read operation.

Abstract: A control circuit for a multiphase buck converter includes a regulator circuit and a plurality of phase control circuits. The regulator circuit generates a regulation signal based on a feedback signal and a reference signal, and each phase control circuit receives a current sense signal and generates a respective PWM signal based on the respective current sense signal and the regulation signal. The control circuit includes a first selector circuit and a second selector circuit configured to receive a selection signal and selectively connect each phase control circuit of a subset of the phase control circuits to a PWM signal for driving a respective stage of the multiphase buck converter, and to a current sense signal provided by the respective stage of the multiphase buck converter. A selection control circuit generates the selection signal in order to connect the phase control circuits to different stages of the multiphase buck converter.