Abstract: Techniques are described for facilitating automation of a self-lifting forklift. According to one or more embodiments, a system is provided that can be located on or within a forklift. The system can comprise a lifting system that provides for vertically lifting or lowering the forklift, a power supply, a memory that stores computer readable and executable components, and a processor that executes the computer readable and executable components stored in the memory. The processor can be operably couple to: a plurality of sensors that sense conditions associated with the forklift, a context component that determines context of the forklift, an analysis component that analyzes information from the plurality of sensors and the context component, and a control component that controls the forklift based on an output from the analysis component, wherein the control includes automatically lifting or lowering of the forklift.

Abstract: Techniques are described for facilitating automation of a self-lifting forklift. According to one or more embodiments, a system is provided that can be located on or within a forklift. The system can comprise a lifting system that provides for vertically lifting or lowering the forklift, a power supply, a memory that stores computer readable and executable components, and a processor that executes the computer readable and executable components stored in the memory. The processor can be operably couple to: a plurality of sensors that sense conditions associated with the forklift, a context component that determines context of the forklift, an analysis component that analyzes information from the plurality of sensors and the context component, and a control component that controls the forklift based on an output from the analysis component, wherein the control includes automatically lifting or lowering of the forklift.

Abstract: Techniques are described for facilitating automation of a self-lifting forklift. According to one or more embodiments, a system is provided that can be located on or within a forklift. The system can comprise a lifting system that provides for vertically lifting or lowering the forklift, a power supply, a memory that stores computer readable and executable components, and a processor that executes the computer readable and executable components stored in the memory. The processor can be operably couple to: a plurality of sensors that sense conditions associated with the forklift, a context component that determines context of the forklift, an analysis component that analyzes information from the plurality of sensors and the context component, and a control component that controls the forklift based on an output from the analysis component, wherein the control includes automatically lifting or lowering of the forklift.

Abstract: A transceiver with non-deterministic delay characteristics is analyzed and adjusted to provide a transceiver with deterministic delay characteristics. The transceiver may be implemented with a variety of device types to support high bandwidth operation over a wide range of frequencies. Deterministic behavior allows use of the transceiver in source synchronous interfaces. The transceiver may also be dynamically analyzed and adjusted during operation as operation frequency changes.

Abstract: Devices which facilitate safe martial arts target striking are disclosed. In an aspect, a hand guard device comprising a blocking surface, a grip, and a stabilizer is disclosed. The hand guard device may assist a holder in holding a striking target, such as a board, while protecting a holder hand from wild blows from an individual attempting to strike the striking target. The hand guard device provides a rigid protective barrier for all portions of the holder hand which would normally be exposed, including the thumb.

Abstract: A processing system (60) includes an input interface (62), a first processor (64), a second processor (66), and an output interface (68) arranged in a serial configuration. Each of the input interface (62), first processor (64), second processor (66), and output interface (68) computes a digest (92, 100, 110, and 114) using information, e.g., a unique parameter (94, 102, 112, 118), known only by that element (62, 64, 66, 68) and using information generated by that element (62, 64, 66, 68). The digests (92, 100, 110, and 114) are used to validate the integrity of payload data (86) processed by the system (60) to form processed data (104) and the system (60) only outputs the processed data (104) upon validation of data integrity. The serial configuration of system (60) may be implemented to provide high bit rate, redundant cryptographic services.

Abstract: Systems and methods efficiently process digests, hashes or other results by performing multiplicative functions in parallel with each other. In various embodiments, successive processing stages are provided, with each stage performing parallel multiplicative functions and also combining input terms to reduce the total number of terms that remain to be processed. By progressively combining the active terms into a smaller number of terms for subsequent processing, the time needed to process a result can be significantly reduced.

Abstract: A method for reliable computation of point additions and point multiplications in an elliptic curve cryptography (ECC) system. Two asymmetric operations are performed: one of the operations is of slightly higher complexity than a conventional ECC operation, and the other operation is of much lower complexity than the first operation. The complexity of the second operation is a function of the desired degree of reliability, or the desired probability of failure detection.

Abstract: A processing system (60) includes an input interface (62), a first processor (64), a second processor (66), and an output interface (68) arranged in a serial configuration. Each of the input interface (62), first processor (64), second processor (66), and output interface (68) computes a digest (92, 100, 110, and 114) using information, e.g., a unique parameter (94, 102, 112, 118), known only by that element (62, 64, 66, 68) and using information generated by that element (62, 64, 66, 68). The digests (92, 100, 110, and 114) are used to validate the integrity of payload data (86) processed by the system (60) to form processed data (104) and the system (60) only outputs the processed data (104) upon validation of data integrity. The serial configuration of system (60) may be implemented to provide high bit rate, redundant cryptographic services.

Abstract: Systems and methods efficiently process digests, hashes or other results by performing multiplicative functions in parallel with each other. In various embodiments, successive processing stages are provided, with each stage performing parallel multiplicative functions and also combining input terms to reduce the total number of terms that remain to be processed. By progressively combining the active terms into a smaller number of terms for subsequent processing, the time needed to process a result can be significantly reduced.

Abstract: A method for reliable computation of point additions and point multiplications in an elliptic curve cryptography (ECC) system. Two asymmetric operations are performed: one of the operations is of slightly higher complexity than a conventional ECC operation, and the other operation is of much lower complexity than the first operation. The complexity of the second operation is a function of the desired degree of reliability, or the desired probability of failure detection.

Abstract: A method for reliable computation of point additions and point multiplications in an elliptic curve cryptography (ECC) system. Two asymmetric operations are performed: one of the operations is of slightly higher complexity than a conventional ECC operation, and the other operation is of much lower complexity than the first operation. The complexity of the second operation is a function of the desired degree of reliability, or the desired probability of failure detection.

Abstract: A method for reliable computation of point additions and point multiplications in an elliptic curve cryptography (ECC) system. Two asymmetric operations are performed: one of the operations is of slightly higher complexity than a conventional ECC operation, and the other operation is of much lower complexity than the first operation. The complexity of the second operation is a function of the desired degree of reliability, or the desired probability of failure detection.

Abstract: A scalable multiplier architecture for the Galois field GF(2k) is implemented in a programmable circuit. This architecture may be used in an implementation of public-key cryptosystems which use programmable multipliers in large Galois fields. This architecture is also fine grain scalable in both the time and the area (or logic) dimensions.