Abstract: In a receiver, a tuner (TUN) converts a reception signal (Srf) to an intermediate-frequency signal (Sif). An adjustable frequency converter (AFRC) converts the intermediate-frequency signal (Sif) to an input signal (Sin) for a filter arrangement (FIL) which is capable of providing various frequency responses (Hfil1, Hfil2) associated with different transmission standards. The adjustable frequency converter (AFRC) and the filter arrangement (FIL) may form part of an integrated receiver-circuit (IRC) suitable for many different transmission standards. The tuner (TUN) may provide the intermediate-frequency signal (Sif) at any one of various different intermediate frequencies (IF1, IF2). For any intermediate frequency (IF1,IF2), the adjustable frequency converter (AFRC) can be adjusted in such a way that the filter arrangement (FIL) receives the input signal (Sin) in a frequency range (FR) which is suitably located with respect to its frequency responses (Hfil1, Hfil2).

Abstract: In a receiver for receiving a modulated carrier (MC) having asymmetrical sidebands (USB,LSB), for example, a TV signal, a synchronous demodulator (SDEM) derives a vectorial baseband signal (VB) from the modulated carrier (MC). A filter (FILT) filters the vectorial baseband signal so as to compensate for the sideband asymmetry, for example, by means of a Nyquist slope. Thus, the sideband asymmetry is compensated at baseband frequencies, rather than at an intermediate frequency, which allows a better quality of reception.

Abstract: To demodulate a quadrature input signal (Si) (for example, frequency shift) a demodulation unit (DEM) is used, comprising a PLL (P) having a complex mixer (M) and a controlled oscillator (V). Normally, a limiter has to be used to keep the loop gain independent of the amplitude of the quadrature input signal. In the PLL, a divider (DEL) is coupled between the mixer (M) and the oscillator (V) to divide the two mixed components (Sm1, Sm2) of the quadrature signal supplied by the mixer.

Abstract: A signal processor has an X-Y rotation circuit and a phase angle control circuit, in the phase angle control circuit, an input phase being approximated by a series of consecutive, in magnitude, decreasing phase angles for forming an output vector by rotation of an input vector over the approximation of the input phase. In the phase angle control circuit, an accuracy of the representation of a phase angle out of the series of phase angles, is dependent on the magnitude of the phase angle, thereby reducing the number of computations in the phase angle control circuit.

Abstract: In a the receiver, a reception signal is digitized (5) with a relatively high sampling frequency. Analog filters (2, 4) prevent aliasing. The digitized reception signal is applied via a splitter (100) to a quadrature digital signal processor (9, 10, 11, 12). In this processor, a desired carrier is selected and demodulated. The splitter (100) transforms the digitized reception signal in accordance with a first and a second transform function (H.sub.1, H.sub.2) to obtain in-phase and quadrature components (xi, yi), respectively. The sampling frequency is reduced (130, 140) in the splitter. A specific relation between the phase and magnitude of the transform functions (H.sub.1, H.sub.2) prevents aliasing. Such a relation can be achieved with relatively simple digital filters (110, 120).

Abstract: Receiver having an A/D converter for digitally sampling an analog signal modulated on a carrier frequency at a first sampling frequency, consecutively coupled to a digital quadrature mixer stage for a carrier frequency shift of the digitized modulated signal from the A/D converter, a digital filter device for selecting the phase quadrature signals of the quadrature mixer stage and for decimating the sampling frequency from the first sampling frequency to a second sampling frequency, and a digital demodulation device.

Abstract: A digital lattice filter, comprising a plurality of identical stages each having a pair of inputs for receiving input signals and a pair of outputs for supplying output signals, these stages being connected in a cascade arrangement, each stage consisting in two mutually linked branches and no less than one of these branches comprising delay means, and in that always an even number of successive cascaded filter stages forms a group, in which both branches of each group of filter stages comprise a delay elements such that the time delay in the first branch is equal to the time delay in the second branch.

Abstract: FM-receiver for receiving an FM-signal with transmission identification. An aerial input is connected to a tuning unit (1) to which there are connected, in succession, an IF-unit (2), an FM-detection circuit (3), a pilot regeneration circuit (10) for regenerating a pilot, a demodulation arrangement (12) for demodulating the code signal which contains transmission identification information, and a clock regeneration circuit (18) which is connected to both the pilot regeneration circuit (10) and the demodulation arrangement (12). The clock regeneration circuit comprises a resettable phase search circuit (18') for producing a clock signal whose frequency is derived from the regenerated pilot and whose phase is derived from the demodulated code signal, a clock-controlled decoding circuit (13) for decoding the code signal and a clock-controlled signal processing unit (17).

Abstract: An FM-receiver with transmitter characterization, having a tuning unit, an IF-amplifier, a demodulation circuit for demodulating a discrete transmitter characterization signal, a clock regeneration circuit, a decoding device for decoding the discrete transmitter characterization signal and a signal processing unit. The clock regeneration circuit regenerates a clock signal the period of which is obtained by dividing the frequency of the stereo pilot signal. Synchronization of the clock signal phase with the phase of the clock signal used in the transmitter is carried out by detecting, using of a periodic window signal, the average phase of the code edges in the discrete transmitter characterization signal and by choosing the phase of the regenerated clock signal to be equal thereto.