Abstract: An Elliptic Curve Cryptography reduction technique utilises a prime number having a first section of Most Significant Word “1” states, with N=nm?1+N1B+n0.

Abstract: An Elliptic Curve Cryptography inversion technique utilises operating on the MSW of four auxiliary variables U, V, R and S with specified invariences.

Abstract: A method and apparatus for calculating the product P of a first number X and a second number Y, modulo N, where Y is partitioned into j words each of length p bits, and has a length (m+n) bits, cyclically operates on successive ones of the j words of Y, carrying out intermediate modulo reductions of the intermediate products formed. A specially selected multiple, N?, of N is used so that only a single reduction of the intermediate based on N? guarantees that the intermediate product P is never longer than (m+n) bits at the end of each cycle. N? is an integer multiple of N, and the value N? is selected such that the (m?1) most significant bits are equal to ‘1’, and the least significant bit is ‘0’.

Abstract: A method of performing encryption or decryption in a cryptographic engine that implements a cryptographic algorithm reduces the risk of differential power analysis revealing key information from inputs and output from S-boxes. The data and address locations used to access the data in S-boxes are encrypted. Retrieval of data from the encrypted S-boxes is effected by performing an address modification function to modify an input address used for a look-up operation to said S-box, and performing a data modification function for modifying data output from said S-box as a result of said look-up operation, the address modification function and the data modification function being selected to compensate for the encryption of the S-box. The S-box encryption and modification functions are periodically updated.

Abstract: An adder circuit for multiplying two long integers deploys a network of adders for summing a succession of words of the long integers to generate intermediate results. The number of addends varies as a function of bit position and the network of adders is designed to reduce the number of levels of adders in the network according to a maximum number of expected addends. A number of strategically placed extra adders may be positioned in the network to further reduce the number of levels. An output stage may be provided that adds sum and carry outputs of the network and retains a most significant bit for use with a subsequent calculation output of the network. The network may be configured so that a subsequent calculation by the network can commence before the previous calculation has been completed, the output of the previous calculation being fed back to the network at an intermediate level and its lowest (output) level.

Abstract: A semiconductor substrate comprises both vertical interconnects and vertical capacitors with a common dielectric layer. The substrate can be suitably combined with further devices to form an assembly. The substrate can be made in etching treatments including a first step on the one side, and then a second step on the other side of the substrate.

Abstract: A method of performing modular multiplication of integers X and Y to produce a result R, where R=X.Y mod N, in a multiplication engine. X is fragmented into a first plurality of words xn each having a first predetermined number of bits, k and Y is fragmented into a second plurality of words yn each having a second predetermined number of bits, m. Multiples of a word xn of X are derived in a pre calculation circuit and subsequently used to derive products of the word xn of X with each of the plurality of words yn of Y. An intermediate result Rj is calculated as a cumulating sum derived from said pre-calculated multiples and the steps repeated for each successive word of X so as to generate successive intermediate results, Rj, for each of the first plurality of words xn. The final result, R is obtained from the last of the intermediate results Rn?1.

Abstract: To provide increased security against differential power analysis attacks, a data processing device is provided with a current converter that draws current from an external supply and cyclically apportions drawn current between a charge storage device and a processor such that the drawn current varies independently of the instantaneous power demand of the processor. The data processing device includes: a processor; a charge storage device coupled to the processor; and a current source for supplying the processor with operating current, and adapted to vary its output current independently of the instantaneous power demand of the processor.

Abstract: Successive round keys of an expanded key according to the AES block cipher algorithm are generated from an initial cryptographic key, for use in a cryptographic (encryption and/or decryption) engine, in real time as the cryptographic process is executing. A limited key memory is used by overwriting previously generated words of the expanded key, leaving only the words of the initial key and the final key in the memory. Thus, a subsequent cryptographic operation can recommence either in the encryption or decryption direction, without delay to the cryptographic engine.

Abstract: A simplified logic circuit for performing the AES Rijndael MixColumns transform exploits the common relationship between each of the successive rows of the transform matrix and its preceding row. A logic circuit for performing multiplication of an (m×n) matrix by a (1×n) or by a (m×1) matrix, where m is a number of rows and n is a number of columns, and where each successive row, m, of n elements is a predetermined row permutation of a preceding row comprises: n multiplication circuits; n logic circuits; n registers for receiving logical output from the logic circuits; feedback logic for routing the contents of each register to a selected one of inputs of the logic circuits in accordance with a feedback plan that corresponds to the common relationship between successive matrix rows; and control means for successively providing as input to each of the n multiplication circuits each element in the (1×n) or (m×1) matrix.