Abstract: A method of creating a three-dimensional image signal comprises receiving a first image component, receiving a second component for creating a three-dimensional image in combination with the first image component, receiving a text component for including in the three-dimensional image, receiving a data component comprising location information describing the location of the text component within the three-dimensional image, and creating a three-dimensional image signal comprising the first image component, the second component, the text component, and the data component. The signal is rendered by rendering a three-dimensional image from the first image component and the second component, the rendering including rendering the text component in the three-dimensional image, the rendering of the text component including adjusting three-dimensional parameters of the three-dimensional image in the location of the rendered text component.

Abstract: A 3-D picture is provided as follows. A pair of pictures (LP, RP) is provided that comprises a first picture (LP) being intended for one eye of a viewer, and a second picture (RP) being intended for the other eye of the viewer. In addition, a depth map (DM) specifically dedicated to the first picture (LP) is provided. The depth map (DM) comprises depth indication values. A depth indication value relates to a particular portion of the first picture (LP) and indicates a distance between an object at least partially represented by that portion of the first picture and the viewer. Such a 3-D picture allows a satisfactory 3-D visual rendering on a great variety of display devices. Preferably, the 3-D picture is supplemented with rendering guidance data (GD) that specifies respective parameters for respective rendering contexts. These respective parameters preferably relate to generating a shifted viewpoint picture from the first picture (LP) and the depth map (DM).

Abstract: An apparatus that contains an instruction processing circuit (14), a main memory (18) addressable by the instruction processing circuit (14) and a cache memory (16). In a normal mode the cache memory (16) is used to cache a part of data and/or instructions that the instruction processing circuit (14) addresses in the main memory (18) during execution, and to substitute cached data and/or instructions when the instruction processing circuit (14) addresses the data and/or instructions in the main memory (18). The circuit is able to switch to a low power operating mode. Upon the switch an interrupt program for executing a function during operation in the low power operating mode is loaded into the cache memory (16) from the main memory (18). Power supply to the main memory (18) is then switched off, but keeping at least a part of the cache memory (16) continuous to receive power supply.