Abstract: In one embodiment, a method comprising receiving a logical signal; driving a source voltage at a first circuit node using a driver circuit; generating an impulsive edge signal by detecting a transition of the logical signal; converting the impulsive edge signal into an impulsive charge pump current using a charge pump circuit; injecting the impulsive charge pump current into the first circuit node; transmitting the source voltage to a second circuit node via a transmission line; and terminating the second circuit node with a load.

Abstract: In one embodiment, a method comprising receiving a logical signal; driving a source voltage at a first circuit node using a driver circuit in accordance with the logical signal; controlling an output impedance of the driver circuit using a finite state machine (FSM); transmitting the source voltage to a second circuit node via a transmission line; and terminating the second circuit node with a load circuit comprising a data detector.

Abstract: A logical transmission system includes a driver configured to receive a source data and output a first voltage at a first node; a transmission line of a characteristic impedance configured to couple the first node to a second node; a three-point three-level slicer configured to receive a second voltage at the second node and output a first ternary signal, a second ternary signal, and a third ternary in accordance with a first reference voltage, a second reference voltage, a first clock, a second clock, and a third clock; and a CDR (clock-data recovery) unit configured to receive a reference clock, the first ternary signal, the second ternary signal, and the third ternary signal and output a recovered data, the first reference voltage, the second reference voltage, the first clock, the second clock, and the third clock.

Abstract: Apparatus and methods are provided for an extraction circuit. In one configuration, an apparatus includes: an edge extraction circuit for receiving a first clock signal and outputting a second clock signal, wherein a duty cycle of the second clock is substantially smaller than a duty cycle of the first clock; a transistor for receiving the second clock signal and outputting a current signal; a transmission line for receiving the current signal on a first end and transmitting the current signal to a second end; a termination circuit for receiving the current signal at the second end and converting the current signal into a voltage signal; and an edge detection circuit for outputting a third clock by detecting an edge of the voltage signal. In one embodiment, the edge detection circuit comprises an inverter. In another embodiment, the edge detection circuit comprises a comparator.