Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. Each processor has a processing element, an input register and an output register, each of which is connected to a segment of the segmented bus system. The segmented bus system provides a plurality of selectable data paths between each processor and other processors, between each processor and each memory and between each memory and other memories.

Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. Each processor has a processing element, an input register and an output register, each of which is connected to a segment of the segmented bus system. The segmented bus system provides a plurality of selectable data paths between each processor and other processors, between each processor and each memory and between each memory and other memories.

Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. A segment is connected to each array processor and each memory whereby a plurality of selectable data paths are provided between each processor and other processors, between each processor and each memory and between each memory and other memories.

Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. A segment is connected to each array processor and each memory whereby a plurality of selectable data paths are provided between each processor and other processors, between each processor and each memory and between each memory and other memories.

Abstract: A data processor chip having a two-dimensional array of arithmetic logic units and memory where the arithmetic logic units are in communication with memory units in one dimension and with other arithmetic units in a second.

Abstract: A data processor chip having a two-dimensional array of arithmetic logic units and memory where the arithmetic logic units are in communication with memory units in one dimension and with other arithmetic units in a second.

Abstract: A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.

Abstract: A parallel processing array processor has a plurality of arithmetic units and a unit that manages barrier instructions whereby processing of program sequences may be coordinated. The array processor further comprises a hierarchy of assigned units whereby multiple program sequences may be processed in parallel.

Abstract: A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.

Abstract: The present invention includes an integrated module including a plurality of data processing units including a memory device having processing instruction data stored therein. The processing instruction data including subconfiguration data for at least one of the data processing units, the subconfiguration data including a plurality of blocks. The integrated module further includes a barrier disposed between a first block and a second block of the plurality of blocks. Wherein, the data processing units process the processing instruction data from the memory device such that the barrier provides for the data processing units to observe a configuration sequence of the subconfiguration data.

Abstract: A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.

Abstract: In a method of synchronizing data processing of processor arrangement, responsive to reaching, during execution of a program, a barrier included in a program sequence, the processor arrangement halts the program execution until it is determined that all instructions preceding the barrier in the program sequence have been successfully scheduled for execution.

Abstract: In a method of synchronizing data processing of processor arrangement, responsive to reaching, during execution of a program, a barrier included in a program sequence, the processor arrangement halts the program execution until it is determined that all instructions preceding the barrier in the program sequence have been successfully scheduled for execution.

Abstract: An example method of controlling a data processing system having a cellular structure. The method includes transmitting a first configuration word to a first processing unit in the cellular structure. The method also includes processing data with the first processing unit in accordance with the first configuration word. The method also includes transmitting a second configuration word to the first processing unit. The method also includes transmitting a reconfiguration signal to the first unit, the reconfiguration signal indicating that the first unit should begin processing data in accordance with the second configuration word. If the first processing unit has completed processing data in accordance with the first configuration word prior to when the reconfiguration signal is received by the first processing unit, data may be processed by the first processing unit in accordance with the second configuration word.

Abstract: A bus system for a configurable architecture and methods therefor are provided in which optimization of the configuration efficiency and reconfiguration efficiency are taken into account separately. A system and method may include controlling data transmission by: transmitting, by a first hardware element and to a second hardware element, a data packet conditional upon and/or responsive to the second hardware element's assignment of a signal to a connecting bus via which the data packet is transmitted, where the signal indicates that no incoming data packet can be lost. A system and method may include controlling data transmission by: transmitting, by a first hardware element and to a second hardware element, a first data packet and subsequently a second data packet; and receiving, by the first hardware element and from the second hardware element, an acknowledgement of the first data packet subsequent to the transmittal of the second data packet.

Abstract: A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.

Abstract: A processor chip includes data processing elements that each has dedicated to it a respective switch for dynamically establishing an interconnection between the data processing elements conditional upon verification of a validity of the interconnection, which verification is automatically performed by at least one of the data processing elements to be interconnected.

Abstract: A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.

Abstract: A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.

Abstract: A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.