Abstract: A variable tracking word recognizer generates an indicating signal when a microprocessor has accessed a memory stack location storing a dynamically addressed variable, the address of the variable being the sum of a dynamically assigned base address of the memory stack and a known address offset where the variable is stored on the stack in relation to the base address. The variable tracking word recognizer stores the dynamically assigned base address, when determined by a space allocation subroutine of a program running on the microprocessor, and then monitors the addresses subsequently appearing on the microprocessor address bus, generating the indicating signal when the current address matches the combination of stored base address and known address offset.

Abstract: An inverse assembly method for converting binary executable microprocessor code into corresponding assembly language mnemonics provides for the storage of all the possible binary codes and corresponding assembly language mnemonics in a plurality of tables set up in a decision tree form which corresponds to the format of a user document provided by the manufacturer of a target microprocessor. The instructions and data information contained within the executable code acquired from the taret microprocessor are distinguishably tagged prior to being stored in an acquisition memory. The code from the acquisition memory, in binary or hex form, indexes a primary table which contains a plurality of entries containing a binary value which may have a mask portion, each entry containing a plurality of actions having an optional string to be displayed, optional parameter masks and an optional table to call.

Abstract: A method for adjusting a time delay of a signal with respect to a reference event is achieved by displaying a graphical representation of the delay time on a display terminal, modifying the displayed graphical depiction to indicate a different time delay, and then adjusting the time delay of the signal to match the modified time delay indicated by the displayed graphical depiction. The display terminal is controlled by a display controller and the graphical depiction of the delay time is modified by an operator using cursor control keys of a keyboard to transmit a first indicating signal to the display controller and other keys of the keyboard to transmit a second indicating signal to the display controller. Each time the controller detects a first indicating signal, the graphically displayed delay time is incremented and each time the controller detects a second indicating signal, the graphically displayed delay time is decremented.

Abstract: An apparatus for time aligning data acquired by one test instrument with corresponding data acquired by another test instrument is disclosed. A set of binary codes, representative of a set of instructions executed by a microprocessor disposed within a user's prototype circuit, are acquired by said one test instrument. With the acquisition of each of said binary codes, a count is developed in a counter indicative of each said acquisition. A multitude of binary data is acquired, independently of the acquisition of the set of binary codes, by said another test instrument, the multitude of binary data being representative of the functions performed by a set of components present within said user's prototype circuit. The binary codes acquired by said one test instrument and the binary data acquired by said another test instrument each have associated therewith a count developed from said counter.

Abstract: A logic analyzer for measuring individually a plurality of logic signals transmitted via a multiplexed digital bus in a time-sharing manner is disclosed. First and second memory circuits store respectively first and second logic signals of the multiplexed digital bus in accordance with first and second strobe signals synchronized with the first and second logic signals.

Abstract: A logic analyzer which can simultaneously measure one block of input data in detail and the same or another block of input data in rough form is disclosed. The logic analyzer comprises first and second sections each including a memory circuit to store the input data and a word recognizer to detect the desired trigger word from the input data. These first and second sections receive different clocks having different rates, and the second memory circuit stores the first clock applied to said first section for recognizing the time relationship of these clock signals. A counter counts the first clock in accordance with the outputs from the first and second word recognizers for recognizing the time relationship of the first and second trigger words.