Abstract: A method for fabricating a self-aligning mask layer includes the steps of forming a surface to be masked in a carrier substrate, the surface having different radii of curvature, forming an undensified conformal insulation layer on the surface such that, on account of the different radii of curvature, regions with different mechanical stress are produced in the insulation layer, and carrying out an etching-back to remove partial regions of the insulation layer in a manner dependent on the different mechanical stress in the insulation layer.

Abstract: The semiconductor structure has an interconnect that is isolated by a cavity from an underlying insulating layer on a support. The fabrication method provides for the interconnect firstly to be patterned on a double layer and to be provided with an insulating covering. Then, an opening is etched into the insulating covering, and the lower conductive layer is selectively removed. As a result, one the one hand, low-capacitance wiring can be fabricated and, on the other hand, this enables MOS transistors to be programmed in a simple manner.

Abstract: The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a substrate (1) with an electrically insulating layer (2) above it; providing an interconnect (WL) having a lower conductive layer (3) and an upper conductive layer (4) on the insulating layer (2), the lower conductive layer (3) consisting of silicon of a first conduction type (n); embedding the interconnect (WL) in an electrically insulating structure (5, 8); reversing the doping of at least one first section (A1; A2) of the lower conductive layer (3) of the interconnect (WL) to the second conduction type (p); and at least partially uncovering a second section (A3) of the lower conductive layer (3) of the interconnect (WL) of the first conduction type (n); and selectively etching the second section (A3) of the lower conductive layer (3) of the interconnect (WL) of the first conduction type (n), with the first section (A1; A2) acting as an etching stop.

Abstract: A method for fabricating a self-aligning mask layer includes the steps of forming a surface to be masked in a carrier substrate, the surface having different radii of curvature, forming an undensified conformal insulation layer on the surface such that, on account of the different radii of curvature, regions with different mechanical stress are produced in the insulation layer, and carrying out an etching-back to remove partial regions of the insulation layer in a manner dependent on the different mechanical stress in the insulation layer.

Abstract: The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a substrate (1) with an electrically insulating layer (2) above it; providing an interconnect (WL) having a lower conductive layer (3) and an upper conductive layer (4) on the insulating layer (2), the lower conductive layer (3) consisting of silicon of a first conduction type (n); embedding the interconnect (WL) in an electrically insulating structure (5, 8); reversing the doping of at least one first section (A1; A2) of the lower conductive layer (3) of the interconnect (WL) to the second conduction type (p); and at least partially uncovering a second section (A3) of the lower conductive layer (3) of the interconnect (WL) of the first conduction type (n); and selectively etching the second section (A3) of the lower conductive layer (3) of the interconnect (WL) of the first conduction type (n), with the first section (A1; A2) acting as an etching stop.

Abstract: The semiconductor structure has an interconnect that is isolated by a cavity from an underlying insulating layer on a support. The fabrication method provides for the interconnect firstly to be patterned on a double layer and to be provided with an insulating covering. Then, an opening is etched into the insulating covering, and the lower conductive layer is selectively removed. As a result, one the one hand, low-capacitance wiring can be fabricated and, on the other hand, this enables MOS transistors to be programmed in a simple manner.

Abstract: The test structure has a row of transistors with at least two transistors. The S/D regions of the transistors are connected in series and the first and the last S/D region in the row can be connected. Possible etching of the gate polysilicon can be ascertained by measuring the resistance between the terminals given a suitable gate potential. The invention enables, in particular, in situ monitoring of a KOH attack on the n-doped gate polysilicon in a DRAM memory cell.