Patents by Inventor Gerd Morsberger
Gerd Morsberger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7961477Abstract: A housing comprising a liquid-tight electric bushing is provided. The housing comprises an opening and a printed circuit board comprising at least first and second layers. The first layer is a top side of the printed circuit board and spans the opening. A first contact element is disposed on the top side and in a blind bore through the first layer that extends to the second layer. The second layer is a conductor track in the interior of the printed circuit board.Type: GrantFiled: December 27, 2004Date of Patent: June 14, 2011Assignee: Siemens AktiengesellschaftInventors: Josef Deuringer, Richard Eichhorn, Lars Lauer, Gerd Mörsberger, Paul Ponnath, Roland Rabe
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Patent number: 7437655Abstract: This invention relates to a flexible rate matching method, comprising the steps of: a) receiving a continuous stream of data items at a prespecified rate of a clock signal in a configurable data shift register; b) storing, for each data item stored in the data shirt register, an associated indication of validity in a configurable validity shift register and shifting the indications of validity at said prespecified rate; c) modifying the contents of the data shift register and the validity shift register through puncture/repetition operations so as to achieve a rate matching, and d) outputting valid data items at said prespecified rate using said indications of validity stored in the validity shift register. The invention also relates to a corresponding flexible rate matching apparatus as well as to a computer program product and a processor program product.Type: GrantFiled: September 18, 2002Date of Patent: October 14, 2008Assignee: Telefonaktiebolaget L M Ericsson (PUBL)Inventors: Gerd Mörsberger, Stefan Schütz, Georg Spörlein
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Patent number: 7269149Abstract: A method for processing a bit sequence in a digital communication system, includes the steps of (a) storing the bits of said bit sequence at locations of a memory means indicated by a first interleaving scheme, (b) converting output bit positions into input bit positions according to an inverse of a second interleaving scheme, (c) reading out bits stored at locations of said memory means corresponding to said input bit positions, thereby generating an interleaved sequence which is interleaved according to said first and said second interleaving schemes, and (d) processing said interleaved sequence according to further physical processing steps. Alternatively, step (a) may include storing the bits of said input bit sequence in a memory means and step (b) may include converting output bit positions into input bit positions according to the inverse of a sequential application of a first interleaving scheme and a second interleaving scheme.Type: GrantFiled: September 24, 2002Date of Patent: September 11, 2007Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Ralf Kukla, Gerd Morsberger, Georg Sporlein, Gerhard Goedert, Edmund Goetz
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Publication number: 20070201216Abstract: A housing comprising a liquid-tight electric bushing is provided. The housing comprises an opening and a printed circuit board comprising at least first and second layers. The first layer is a top side of the printed circuit board and spans the opening. A first contact element is disposed on the top side and in a blind bore through the first layer that extends to the second layer. The second layer is a conductor track in the interior of the printed circuit board.Type: ApplicationFiled: December 27, 2004Publication date: August 30, 2007Inventors: Josef Deuringer, Richard Eichhorn, Lars Lauer, Gerd Morsberger, Paul Ponnath, Roland Rabe
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Patent number: 7091889Abstract: This invention relates to a method for interleaving, according to an interleaving scheme, an input sequence comprising K bits into an interleaved sequence, comprising the steps of (a) storing the input sequence in a first memory means, (b) generating first indices of N succeeding bits of the interleaved sequence, wherein 1 m(F) N m(F) K, (c) converting. according to an inverse of said interleaving scheme, said first indices into second indices indicative of the positions where said N succeeding bits of the interleaved sequence are stored in said first memory means, and (d) reading out said N succeeding bits from said positions in said first memory means, thereby generating at least part of said interleaved sequence.Type: GrantFiled: September 9, 2002Date of Patent: August 15, 2006Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Ralf Kukla, Stefan Schütz, Georg Spörlein, Gerd Mörsberger
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Publication number: 20060140142Abstract: A method for processing a bit sequence in a digital communication system, includes the steps of (a) storing the bits of said bit sequence at locations of a memory means indicated by a first interleaving scheme, (b) converting output bit positions into input bit positions according to an inverse of a second interleaving scheme, (c) reading out bits stored at locations of said memory means corresponding to said input bit positions, thereby generating an interleaved sequence which is interleaved according to said first and said second interleaving schemes, and (d) processing said interleaved sequence according to further physical processing steps. Alternatively, step (a) may include storing the bits of said input bit sequence in a memory means and step (b) may include converting output bit positions into input bit positions according to the inverse of a sequential application of a first interleaving scheme and a second interleaving scheme.Type: ApplicationFiled: September 24, 2002Publication date: June 29, 2006Inventors: Ralf Kukla, Gerd Morsberger, Georg Sporlein, Gerhard Goedert, Edmund Goetz
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Publication number: 20050248473Abstract: This invention relates to a method for interleaving, according to an interleaving scheme, an input sequence comprising K bits into an interleaved sequence, comprising the steps of (a) storing the input sequence in a first memory means, (b) generating first indices of N succeeding bits of the interleaved sequence, wherein 1 m(F) N m(F) K, (c) converting, according to an inverse of said interleaving scheme, said first indices into second indices indicative of the positions where said N succeeding bits of the inter-leaved sequence are stored in said first memory means, and (d) reading out said N succeeding bits from said positions in said first memory means, thereby generating at least part of said interleaved sequence.Type: ApplicationFiled: September 9, 2002Publication date: November 10, 2005Inventors: Ralf Kukla, Stefan Schutz, Georg Sporlein, Gerd Morsberger
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Publication number: 20050105605Abstract: This invention relates to a flexible rate matching method, comprising the steps of: a) receiving a continuous stream of data items at a prespecified rate of a clock signal in a configurable data shift register; b) storing, for each data item stored in the data shirt register, an associated indication of validity in a configurable validity shift register and shifting the indications of validity at said prespecified rate; c) modifying the contents of the data shift register and the validity shift register through puncture/repetition operations so as to achieve a rate matching, and d) outputting valid data items at said prespecified rate using said indications of validity stored in the validity shift register. The invention also relates to a corresponding flexible rate matching apparatus as well as to a computer program product and a processor program product.Type: ApplicationFiled: September 18, 2002Publication date: May 19, 2005Inventors: Gerd Morsberger, Stefan Schutz, Georg Sporlein
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Patent number: 6651209Abstract: A turbo coder block having a parallelization of degree n achieves increased processing speed. Each parallelized turbo coder block includes a first storage unit to store n samples of an input signal and a second storage unit to store n samples of at least one output signal of the parallelized turbo coding block. The parallelized turbo coder block further includes a bank of n delay units and is adapted to parallel process n samples of the input signal such that two delay units of the bank directly receive subsets of the n samples of the input signal, and an output signal of one delay unit is supplied to two delay units in the parallelized turbo coder block.Type: GrantFiled: September 12, 2000Date of Patent: November 18, 2003Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Gerd Mörsberger, Georg Sporlein
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Patent number: 6560746Abstract: The invention relates to a parallel CRC generation circuit comprising an input register means (I), an output register means (C), a number of XOR gates (XOR1-XORN) and a coupling means (CM) that feeds predetermined ones of the output lines (C0-CN−1) of the output register means (C) and output lines (I1-In) of the input register means (I) as inputs to the respective XOR gates. According to the invention a matrix representation of the state change based on the selected CRC polynomial is set up and evaluated, such that the coupling means (CM) only uses the minimum number of feedbacks of the output lines and feed-forwards of the output lines of the input register means (I). Thus, the parallel CRC calculation circuit according to the invention has no redundancy and uses only a minimum hardware amount.Type: GrantFiled: August 25, 1999Date of Patent: May 6, 2003Assignee: Telefonaktiebolaget LM EricssonInventor: Gerd Mörsberger
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Patent number: 6556618Abstract: In a telecommunication system where a plurality of user channels are processed in a time-slotted manner, a transmitter and receiver can perform bit error rate measurements for a plurality of user channels by only using one PN-generator (T-PN) and one state memory (ISM). Whenever the beginning of a new time-slot is detected, a last-stored phase state is read out from the state memory (ISM). When detecting the end of the respective time-slot, the phase state then present in the PN-generator (T-PN) is stored into the state memory (ISM) to be used for re-initialization of the PN-generator (T-PN) for the same time-slot in a succeeding frame. Thus, one PN-generator (T-PN) is enough for generating PN-sequences for a great number of user channels.Type: GrantFiled: August 25, 1999Date of Patent: April 29, 2003Assignee: Telefonaktiebolaget LM EricssonInventors: Gerd Mörsberger, Gian Huaman-Bollo, Helmut Leuschner