Abstract: A digital phase-locked loop (PLL) which responds to a square-wave input signal of on expected frequency f.sub.E and comprises a change-over switch which is switched in response to square-wave signals or different frequencies and precedes a main divider operating with a divisor D and which produces the output signal of the phase-locked loop. The change-over switch is activated as a function of the output signal and the input signal. In order to provide symmetrical locking in of the phase-locked loop and a small capture-and-hold range, the change-over switch is switched between a first square-wave signal of the frequency f.sub.1, a second square-wave signal of the second frequency f.sub.2 and a third square-wave signal of the frequency f.sub.3, in which:f.sub.1 .multidot.1/D=f.sub.Eandk.multidot.f.sub.1 =f.sub.2 +(k-1).multidot.f.sub.3,A switching logic is provided which controls the change-over switch in such that it is switched to the signal of the first frequency f.sub.

Abstract: Circuitry for processing, in a television signal, a first, low-frequency synchronizing signal on which a second, high-frequency synchronizing signal is superposed, for supplying standardized television signal capable of being processed by a customary television signal processing arrangement or display device, respectively by inhibiting a shift between the picture content of the signal representing the television signal and the synchronizing signal.

Abstract: A circuit arrangement for transferring a d.c. voltage via a smoothing network including a capacitor which can be switched to prevent a surge in the transferred signal from occurring. The voltage from the output terminal is applied to the capacitor in the changed-over state via an amplifier having a high input impedance and a gain factor of substantially 1.

Abstract: A push-pull B-stage in IC is arranged with an additional transistor in such a manner that one transistor in the IC and the additional transistor together constitute a new push-pull amplifier while the transistor in the IC is loaded to a higher extent and the other final stage transistor in the IC only serves as a driver for the additional transistor.