Abstract: A device having an integrated circuit and a circuit package. A first terminal contact, a second terminal contact, and a third terminal contact are brought out of the circuit package. The first terminal contact and the second terminal contact are each connected to terminals of the integrated circuit for power supply. The third terminal contact is connected to a terminal of the integrated circuit in the circuit package for signal transmission. A first capacitor is connected to the first terminal contact and a second capacitor is connected to the third terminal contact, wherein a fourth terminal contact and a fifth terminal contact are brought out of the circuit package, and the first capacitor is connected to the fourth terminal contact, and the second capacitor is connected to the fifth terminal contact.

Abstract: An inventive device for simultaneous testing of a plurality of integrated circuits is described. Each integrated circuit of the plurality of integrated circuits includes a test mode, wherein a test sequence is executed in the integrated circuits, as well as a pin for outputting test data produced in the test mode. The device includes a plurality of test interfaces adapted to be connected with the pin of the plurality of integrated circuits, for receiving the test data of the plurality of integrated circuits, an interface adapted to be connected to a synchronization interface of an integrated reference circuit, wherein a test sequence is executed which is identical with the test sequence of the plurality of integrated circuits, for receiving a synchronization signal which is synchronous with the test sequence, and synchronization means for synchronizing the simultaneous testing on the basis of the synchronization signal of the integrated reference circuit.

Abstract: An inventive device for simultaneous testing of a plurality of integrated circuits is described. Each integrated circuit of the plurality of integrated circuits includes a test mode, wherein a test sequence is executed in the integrated circuits, as well as a pin for outputting test data produced in the test mode. The device includes a plurality of test interfaces adapted to be connected with the pin of the plurality of integrated circuits, for receiving the test data of the plurality of integrated circuits, an interface adapted to be connected to a synchronization interface of an integrated reference circuit, wherein a test sequence is executed which is identical with the test sequence of the plurality of integrated circuits, for receiving a synchronization signal which is synchronous with the test sequence, and synchronization means for synchronizing the simultaneous testing on the basis of the synchronization signal of the integrated reference circuit.