Abstract: The invention relates to a method for producing vertical electrical connections (micro-vias) in semiconductor wafers for the fabrication of semiconductor components. The method is characterized by the following steps: —application of a protective resist to the wafer front side—patterning of the protective resist on the wafer front side such that the contacts to be connected to the wafer rear side become free—laser drilling of passage holes at the contact connection locations from the wafer rear side through the semiconductor substrate, the active layers and the contacts to be connected on the wafer front side—cleaning of the wafer (debris removal)—application of a plating base to the wafer rear side and into the laser-drilled passage holes—application of gold by electrodeposition onto the metallized wafer rear side and the passage holes—resist stripping of the protective resist—application of an antiwetting layer in the region of the entrance openings of the passage holes at the wafer rear side.