Patents by Inventor Gerd Spalink

Gerd Spalink has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7016446
    Abstract: A channel decoder for a digital broadcast receiver having a synchronization byte detector for detecting synchronization bytes in a decoded transmission signal. The synchronization byte detector provides a synchronization signal indicating a start of frame for transport stream packets in the decoded transmission signal and provides a lock detected output signal indicating the lock-in of the receiver to one broadcast channel. The lock detected output signal is used as at least one of a feed forward signal and a feed back signal to switch processing stages at least one of succeeding and preceding, respectively, said synchronization byte detector into a different mode dependent on whether or not a lock has been achieved.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: March 21, 2006
    Assignee: SONY International (Europe) GmbH
    Inventor: Gerd Spalink
  • Publication number: 20050177626
    Abstract: A system (1) for storing and rendering multimedia data comprises: a multimedia content archive (2) for storing multimedia data files (10, 13) to be rendered, a transforming algorithm archive (3) for storing transforming algorithm description files (12, 14, 15) comprising information for transforming multimedia data file (10, 13) of a first format into multimedia data files of a second format, respectively, wherein each stored multimedia data file (10, 13) is individually linked to at least one of said transforming algorithm description files (12, 14, 15), at least one rendering device (4a, 4b) being connected to said multimedia content archive (2) and said transforming algorithm archive (3), said at least one rendering device (4a, 4b) being capable of rendering a specific multimedia data file (10, 13) in dependence of transforming algorithm description files (12, 14, 15), to which said specific multimedia data file (10, 13) is linked to, respectively.
    Type: Application
    Filed: February 4, 2005
    Publication date: August 11, 2005
    Inventors: Volker Freiburg, Gerd Spalink, Peter Wagner
  • Publication number: 20050169386
    Abstract: A Method for pre-processing digital data and in particular of pre-processing digital video and/or digital audio data is provided, wherein a step of encoding (S3) a primary data stream (D1), a step of encrypting (S4) an encoded primary data stream (ED1) and a process of generating (P3) a preview data stream (PD) are built in and/or embedded within a common process (P2) of encoding said primary data stream (D1) in particular by integrating these processes and/or steps within a single and common encoder. The present invention additionally relates to a conversion system (10, 20) having a conversion functionality (11, 21) and a logic functionality (12, 22). Key aspect of the present invention is that said conversion functionality (11, 21) and said logic functionality (12, 22) are embedded in one single and common unit.
    Type: Application
    Filed: January 12, 2005
    Publication date: August 4, 2005
    Inventors: Gerd Spalink, Volker Freiburg, Peter Wagner
  • Patent number: 6920189
    Abstract: The present invention relates to a carrier recovery means in particular in a channel decoding unit or a digital demodulating unit of a digital broadcasting receiver. The inventive carrier recovery means comprises at least first and second phase error detecting means (2, 4) in which the first phase error detecting means (2) generates a robust phase error signal based on a digital input signal. Said second phase error detecting means (4) receives said robust phase error signal and generates therefrom a frequency sensitive phase error signal which is representative for the frequency error or frequency offset between the frequency of the receiver and the frequency of the carrier of the received digital input signal. The frequency sensitive phase error signal is then used to reduce at least the frequency error with respect to the received digital input signal to enable locking of the receiver to the carrier of the digital signal.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: July 19, 2005
    Assignee: Sony International (Europe) GmbH
    Inventor: Gerd Spalink
  • Patent number: 6816560
    Abstract: A packet synchronization detector for an incoming digital signal which includes a regularly repeated predetermined synchronization pattern which repetition rate defines the length of one transmission packet according to the present invention comprises a synchronization pattern detector (1) and several synchronization state machines (2, 31, . . . , 3n) which respectively determine whether or not one detected synchronization pattern with a respective position in regard to the length of one transmission frame has the correct repetition rate to determine whether or not lock has been achieved. Therefore, a very fast lock is achieved, since also in case of bit patterns that match to the synchronization byte, but that are not the synchronization byte no penalty time occurs to lock to the incoming digital signal.
    Type: Grant
    Filed: July 5, 2000
    Date of Patent: November 9, 2004
    Assignee: Sony International (Europe) GmbH
    Inventor: Gerd Spalink
  • Publication number: 20040157580
    Abstract: In a method for operating an RLAN arrangement (1) having a plurality of communication units (10, 20), wherein a step of monitoring the presence or occurrence of signals from external radar sources (100) is performed by at least one of said communication units being not in a transmission state as a monitoring unit, thereby realizing a continuous and uninterrupted monitoring of a presence of signals of external radar sources (100) over the complete operation time of the RLAN arrangement (1).
    Type: Application
    Filed: January 26, 2004
    Publication date: August 12, 2004
    Inventors: Lothar Stadelmeier, Frank Dawidowsky, Heimo Guth, Gerd Spalink, Jens Hofflinger
  • Publication number: 20040057461
    Abstract: For a connection of a network requiring a certain quality of service (QoS), i.e. a QoS connection, generally a fixed amount of bandwidth is allocated. In prior art networks this fixed amount of bandwidth cannot be used by other connections. Therefore, in case the QoS connection does not require all of the allocated fixed amount of bandwidth, bandwidth may be wasted. The present invention provides a method that enables the use of bandwidth, that is currently not used by a QoS connection. This currently unused bandwidth is temporarily freed, such that other connections may use this freed bandwidth. In case all or parts of the freed bandwidth is needed again by the connection, the bandwidth is re-allocated to the connection immediately.
    Type: Application
    Filed: September 4, 2003
    Publication date: March 25, 2004
    Inventors: Frank Dawidowsky, Jens Hofflinger, Gerd Spalink, Lothar Stadelmeier
  • Publication number: 20030135730
    Abstract: A content protection and copy management system for a network is proposed which comprises at least one conditional access module within the network, respectively adapted to receive at least one encrypted content stream through the network, to decrypt a respective received encrypted content stream, and to apply a secure link encryption to each decrypted content stream before outputting it to the network.
    Type: Application
    Filed: October 17, 2002
    Publication date: July 17, 2003
    Inventors: Paul Szucs, Gerd Spalink, Andreas Schwager, Richard Barry, Masahiko Sato
  • Publication number: 20030084225
    Abstract: The inventive interface link layer device is connected in-between a first sub network and a long delay link to which at least one second sub network is connected. The interface link layer device comprises at least two storage means, whereby new configuration data received via the long delay link is written to one of said storage means to simulate the devices of the second network within the first network. As long as the configuration information is not complete yet, the respective other storage means are accessed in case a self ID phase is initiated. In case a self ID phase is initiated as soon as or after the new configuration data is complete, the storage means to which the new configuration data has been written is used for setting up the self ID packets.
    Type: Application
    Filed: October 23, 2002
    Publication date: May 1, 2003
    Inventors: Gralf Gadeken, Gerd Spalink
  • Publication number: 20020041607
    Abstract: A method to perform a cycle synchronization between several interconnected sub-networks, comprises the steps that a reference node connected to one of the sub-networks transmits a respective cycle time information to cycle masters of all other sub-networks at recurring time instants, and the cycle masters of all other sub-networks adjust their cycle time accordingly. Therefore, a cycle synchronizator comprises a clock offset estimation means (1) to determine a timing error of an own cycle timer (3), and a cycle adjustment loop (2) receiving the timing error determined by said clock offset estimation means (1) to adjust the own cycle timer (3) to reduce its timing error.
    Type: Application
    Filed: October 5, 2001
    Publication date: April 11, 2002
    Inventor: Gerd Spalink
  • Publication number: 20010026557
    Abstract: An interface link layer device (1) of an interface which allows the interconnection of different networks to build a distributed network according to the present invention routes complete data packets directly to another interface link layer device (1) that serves the destination via uplink means (10, 11, 12, 13, 14, 17) to accept a data packet from a first data bus (2) that has a predetermined destination on a second data bus and to transmit it via said transmission path (3) to said other interface link layer device (1), and downlink means (20, 21) to output data packets received via said transmission path (3) from one other interface link layer device (1) to a predetermined destination on the first data bus (2).
    Type: Application
    Filed: December 29, 2000
    Publication date: October 4, 2001
    Inventors: Gralf Gaedeken, Peter Buchner, Gerd Spalink
  • Publication number: 20010023452
    Abstract: An interface link layer device (1) to be connected in-between a first sub network (5) and a long delay link (3) to which at least one second sub network (4) is connected via another interface link layer device (2) is able to simulate or replace time critical messages of the at least one second sub network (4). To set-up a network with such interface link layer devices information about the configuration of the sub network (5; 4) connected to an interface link layer device (1; 2) is transmitted from said respective interface link layer device (1; 2) to all other interface link layer devices (2; 1) connected to said respective interface link layer device (1; 2) via the long delay link (3), whereafter a respective interface link layer device (2; 1) connected thereto which received information about the configuration of at least one other sub network (5; 4) is able to perform the neccessary simulation.
    Type: Application
    Filed: March 6, 2001
    Publication date: September 20, 2001
    Inventors: Gerd Spalink, Gralf Gaedeken, Peter Buchner
  • Patent number: 6226333
    Abstract: According to the invention, information from a differential decoder (1) receiving the MSB of the in-phase component and the MSB of the quadrature component is used to derotate the LSBs of the in-phase component and the LSBs of the quadrature component into the first quadrant with a rotator (2). Then only one quadrant is demapped by a single quadrant demapper (3). Thereby, the look-up table necessary for the demapping circuit is reduced considerably. The output signal of the QAM de-mapping circuit is build from the demapped LSBs of the in-phase and quadrature components output by the single quadrant demapper (3) and the outputs of the differential decoder (1).
    Type: Grant
    Filed: August 3, 1998
    Date of Patent: May 1, 2001
    Assignee: Sony International (Europe) GmbH
    Inventor: Gerd Spalink
  • Patent number: 5532753
    Abstract: An audio and/or video reproducing apparatus receives broadcast signals from broadcasting stations and a/v signals from an external device; processes the audio and/or video input signals in accordance with multiple processing functions; selects audio and/or video input signals for reproduction; reproduces sound and/or a video picture corresponding to the selected audio and/or video input signals; and includes a pointing device and a control device for generating a control picture signal and controlling the processing of signals and a display device for displaying a control picture corresponding to the control picture signal. The control picture includes a plurality of control areas and a pointer movable within the control picture in response to operation of the pointing device, with identifications of the broadcasting stations and the external device provided within certain control areas.
    Type: Grant
    Filed: March 18, 1994
    Date of Patent: July 2, 1996
    Assignee: Sony Deutschland GmbH
    Inventors: Peter Buchner, Gerd Spalink