Patents by Inventor Gerd von Colln

Gerd von Colln has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Predictable design of low power systems by pre-implementation estimation and optimization
    Patent number: 7725848
    Abstract: A method of designing a low power circuit that implements specified functionality, the method including: analyzing code for an algorithmic description of the specified functionality to generate a design representation of the circuit at the algorithmic level; instrumenting the code for the algorithmic description so as to capture data streams during execution/simulation of the algorithmic description; executing/simulating the instrumented code to generate an activity profile for the algorithmic description, wherein said activity profile includes at least portions of data traces of at least a portion of the executed algorithmic description; using the design representation to generate an initial hardware design that is an estimate of hardware resources necessary to implement at least some of the specified functionality; and computing power consumption for the initial hardware design based on the activity profile and power models for the hardware resources.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: May 25, 2010
    Inventors: Wolfgang Nebel, Ansgar Stammermann, Domenik Helms, Eike Schmidt, Milan Schulte, Lars Kruse, Gerd von Cölln, Arne Schulz
  • Predictable design of low power systems by pre-implementation estimation and optimization
    Publication number: 20050204316
    Abstract: A method of designing a low power circuit that implements specified functionality, the method including: analyzing code for an algorithmic description of the specified functionality to generate a design representation of the circuit at the algorithmic level; instrumenting the code for the algorithmic description so as to capture data streams during execution/simulation of the algorithmic description; executing/simulating the instrumented code to generate an activity profile for the algorithmic description, wherein said activity profile includes at least portions of data traces of at least a portion of the executed algorithmic description; using the design representation to generate an initial hardware design that is an estimate of hardware resources necessary to implement at least some of the specified functionality; and computing power consumption for the initial hardware design based on the activity profile and power models for the hardware resources.
    Type: Application
    Filed: January 27, 2005
    Publication date: September 15, 2005
    Applicant: ChipVision Design Systems AG
    Inventors: Wolfgang Nebel, Ansgar Stammermann, Domenik Helms, Eike Schmidt, Milan Schulte, Lars Kruse, Gerd von Colln, Arne Schulz