Abstract: The present disclosure provides a semiconductor device structure including an active region having a semiconductor-on-insulator (SOI) configuration, a semiconductor device of lateral double-diffused MOS (LDMOS) type, a dual ground plane region formed by two well regions which are counter-doped to each other, the dual ground plane region extending below the semiconductor device, and a deep well region extending below the dual ground plane region. Herein, the semiconductor device of LDMOS type comprises a gate structure formed on the active region, a source region and a drain region formed in the active region at opposing sides of the gate structure, and a channel region and a drift region, both of which being formed in the active region and defining a channel drift junction, wherein the channel drift junction is overlain by the gate structure.

Abstract: The present disclosure provides a semiconductor device structure including an active region having a semiconductor-on-insulator (SOI) configuration, a semiconductor device of lateral double-diffused MOS (LDMOS) type, a dual ground plane region formed by two well regions which are counter-doped to each other, the dual ground plane region extending below the semiconductor device, and a deep well region extending below the dual ground plane region. Herein, the semiconductor device of LDMOS type comprises a gate structure formed on the active region, a source region and a drain region formed in the active region at opposing sides of the gate structure, and a channel region and a drift region, both of which being formed in the active region and defining a channel drift junction, wherein the channel drift junction is overlain by the gate structure.

Abstract: A method of forming a semiconductor device is provided, wherein the method includes forming a shaped gate structure over an active region, the shaped gate structure comprising a gate dielectric layer and a gate electrode disposed on the gate dielectric layer, and forming raised source/drain regions adjacent to the gate structure, the raised source/drain regions being formed at opposing sides of the shaped gate structure relative to a length direction of the shaped gate structure, wherein the gate electrode has a tapering shape according to which a dimension of the gate electrode along the length direction varies from a maximum value at a lower portion of the gate electrode close to the gate dielectric layer towards a minimal value at a top portion of the gate electrode.

Abstract: Integrated circuits having resistor structures formed from gate metal and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a transistor area. The method deposits a gate metal over the resistor area and the transistor area of the semiconductor substrate, and the gate metal forms a gate metal layer in the resistor area. The method includes etching the gate metal to form a resistor structure from the gate metal layer in the resistor area. Further, the method includes forming contacts to the resistor structure in the resistor area.

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a stack overlying a substrate. The stack includes a silicon germanium layer and a silicon layer, where the silicon germanium layer has a first germanium concentration. The stack is condensed to produce a second germanium concentration in the germanium layer, where the second germanium concentration is greater than the first germanium concentration. A fin is formed that includes the stack, and a gate is formed overlying the fin.

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a stack overlying a substrate. The stack includes a silicon germanium layer and a silicon layer, where the silicon germanium layer has a first germanium concentration. The stack is condensed to produce a second germanium concentration in the germanium layer, where the second germanium concentration is greater than the first germanium concentration. A fin is formed that includes the stack, and a gate is formed overlying the fin.

Abstract: A semiconductor product with certain devices having a first device with a fully silicided (FuSi) gate and a second device with a partially silicided gate is disclosed. In one example, the first semiconductor device is recessed, resulting in a recessed first gate electrode material which is fully silicided during a subsequent silicidation process. On the gate electrode material of the second semiconductor device, a silicide portion is formed above a layer of polysilicon or amorphous silicon during the silicidation process.

Abstract: A semiconductor device includes a semiconductor material positioned above a substrate and a gate structure positioned above a surface of the semiconductor material, the gate structure covering a non-planar surface portion of the surface. A sidewall spacer is positioned adjacent to the gate structure and includes first dopants having one of an N-type and a P-type conductivity, wherein the sidewall spacer covers an entire sidewall surface of the gate structure and partially covers the surface of the semiconductor material. Source/drain extension regions that include the first dopants are positioned within the non-planar surface portion and in alignment with the sidewall spacer, wherein a concentration of the first dopants within a portion of the sidewall spacer proximate the non-planar surface portion substantially corresponds to a concentration of the first dopants within the source/drain extension regions proximate the non-planar surface portion.

Abstract: The present disclosure provides a method of forming a semiconductor device structure with selectively fabricating semiconductor device structures having fully silicided (FuSi) gates and partially silicided gates. In aspects of the present disclosure, a semiconductor device structure with a first semiconductor device and a second semiconductor device is provided, wherein each of the first and second semiconductor devices includes a gate structure over an active region, each of the gate structures having a gate electrode material and a gate dielectric material. The gate electrode material of the first semiconductor device is recessed, resulting in a recessed first gate electrode material which is fully silicided during a subsequent silicidation process. On the gate electrode material of the second semiconductor device, a silicide portion is formed during the silicidation process.

Abstract: Methods for forming gates without spacers and the resulting devices are disclosed. Embodiments may include forming a channel layer on a substrate; forming a dummy gate on the channel layer; forming an interlayer dielectric (ILD) on the channel layer and surrounding the dummy gate; forming a trench within the ILD and the channel layer by removing the dummy gate and the channel layer below the dummy gate; forming an un-doped channel region at the bottom of the trench; and forming a gate above the un-doped channel region within the trench.

Abstract: The present disclosure provides a method of forming a semiconductor device structure with selectively fabricating semiconductor device structures having fully silicided (FuSi) gates and partially silicided gates. In aspects of the present disclosure, a semiconductor device structure with a first semiconductor device and a second semiconductor device is provided, wherein each of the first and second semiconductor devices includes a gate structure over an active region, each of the gate structures having a gate electrode material and a gate dielectric material. The gate electrode material of the first semiconductor device is recessed, resulting in a recessed first gate electrode material which is fully silicided during a subsequent silicidation process. On the gate electrode material of the second semiconductor device, a silicide portion is formed during the silicidation process.

Abstract: Methods for forming gates without spacers and the resulting devices are disclosed. Embodiments may include forming a channel layer on a substrate; forming a dummy gate on the channel layer; forming an interlayer dielectric (ILD) on the channel layer and surrounding the dummy gate; forming a trench within the ILD and the channel layer by removing the dummy gate and the channel layer below the dummy gate; forming an un-doped channel region at the bottom of the trench; and forming a gate above the un-doped channel region within the trench.

Abstract: Methods for forming a vertical capacitance structure and the resulting devices are disclosed. Embodiments may include forming fins on a substrate; conformally forming a first metal layer over the fins; conformally forming an insulation layer over the first metal layer; and forming a second metal layer over the insulation layer.

Abstract: Integrated circuits having improved contacts and improved methods for fabricating integrated circuits having contacts are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a source/drain region. The method deposits an interlayer dielectric material over the semiconductor substrate. Further, the method etches the interlayer dielectric material to form a hole defining an exposed portion of the source/drain region. The method includes forming a contact forming a contact in the hole over the exposed portion of the source/drain region and forming an interconnect in the hole over the contact.

Abstract: When forming field-effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art, which may overcome this problem. However, formation of a fully silicided gate is hindered by the fact that silicidation of the source and drain regions and of the gate electrode are normally performed simultaneously. The claimed method proposes two consecutive silicidation processes which are decoupled with respect to each other. During the first silicidation process, a metal silicide is formed forming an interface with the source and drain regions and without affecting the gate electrode. During the second silicidation, a metal silicide layer having an interface with the gate electrode is formed, without affecting the transistor source and drain regions.

Abstract: A method of forming a transistor device is provided, including the subsequently performed steps of forming a gate electrode on a first semiconductor layer, forming an interlayer dielectric over the gate electrode and the first semiconductor layer, forming a first opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on one side of the gate electrode and a second opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on another side of the gate electrode, the first and second openings reaching to the first semiconductor layer, forming cavities in the first semiconductor layer through the first and second openings formed in the interlayer dielectric, and forming embedded second semiconductor layers in the cavities.

Abstract: The present disclosure provides in various aspects methods of forming a semiconductor device, methods for forming a semiconductor device structure, a semiconductor device and a semiconductor device structure. In some illustrative embodiments herein, a gate structure is formed over a non-planar surface portion of a semiconductor material provided on a surface of a substrate. A doped spacer-forming material is formed over the gate structure and the semiconductor material and dopants incorporated in the doped spacer-forming material are diffused into the semiconductor material close to a surface of the semiconductor material so as to form source/drain extension regions. The fabricated semiconductor devices may be multi-gate devices and, for example, comprise finFETs and/or wireFETs.

Abstract: A method of forming a transistor device is provided, including the subsequently performed steps of forming a gate electrode on a first semiconductor layer, forming an interlayer dielectric over the gate electrode and the first semiconductor layer, forming a first opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on one side of the gate electrode and a second opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on another side of the gate electrode, the first and second openings reaching to the first semiconductor layer, forming cavities in the first semiconductor layer through the first and second openings formed in the interlayer dielectric, and forming embedded second semiconductor layers in the cavities.

Abstract: Integrated circuits having resistor structures formed from gate metal and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a transistor area. The method deposits a gate metal over the resistor area and the transistor area of the semiconductor substrate, and the gate metal forms a gate metal layer in the resistor area. The method includes etching the gate metal to form a resistor structure from the gate metal layer in the resistor area. Further, the method includes forming contacts to the resistor structure in the resistor area.

Abstract: When forming field-effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art, which may overcome this problem. However, formation of a fully silicided gate is hindered by the fact that silicidation of the source and drain regions and of the gate electrode are normally performed simultaneously. The claimed method proposes two consecutive silicidation processes which are decoupled with respect to each other. During the first silicidation process, a metal silicide is formed forming an interface with the source and drain regions and without affecting the gate electrode. During the second silicidation, a metal silicide layer having an interface with the gate electrode is formed, without affecting the transistor source and drain regions.