Abstract: A data processing apparatus includes a plurality of power domains controlled by respective power control signals PCS. Power control circuitry includes mapping circuitry which maps a plurality of power status signals PSS indicative of the power status of respective power domains, and received from those power domains, to form the power control signals which are then supplied power domains. The mapping circuitry may be controlled by mapping parameters stored within a memory mapped array. The mapping parameters may specify that a given power control signal is either sensitive or insensitive to the power status of a particular other power domain within the data processing apparatus-2. The mapping parameters may be fixed or software programmable.

Abstract: A system and method are provided for controlling a reset procedure. The system has a plurality of power domains, where each power domain comprises a plurality of components, and a plurality of power controllers, wherein each power controller has at last one associated power domain and is arranged to control a supply of power to each associated power domain. The plurality of power controllers are arranged in a hierarchical arrangement comprising two or more hierarchical levels. A given power controller at a given hierarchical level is arranged to implement a reset procedure requiring a reset to be performed in a given reset domain, where the given reset domain comprises at least a subset of the components provided in multiple power domains associated with multiple power controllers provided in at least one hierarchical level below the given hierarchical level.

Abstract: A system and method are provided for controlling power mode transitions. The system has a plurality of power domains, where each power domain has one or more components, and a plurality of power controllers, where each power domain is associated with one of the power controllers. For each power domain, the associated power controller controls transition of that power domain between a plurality of power modes. The power controllers are connected by communication links in order to implement a hierarchical relationship between the power controllers that comprises two or more hierarchical levels. Each power controller other than a highest level power controller in the hierarchical relationship is connected by a communication link to an associated higher level power controller at a higher hierarchical level in the hierarchical relationship.

Abstract: The system has a plurality of power domains, where each power domain has one or more components, and a plurality of power controllers, where each power domain is associated with one of the power controllers. For each power domain, the associated power controller controls transition of that power domain between a plurality of power modes. The power controllers are connected by communication links in order to implement a hierarchical relationship between the power controllers that comprises two or more hierarchical levels. Each power controller other than a highest level power controller in the hierarchical relationship is connected by a communication link to an associated higher level power controller at a higher hierarchical level in the hierarchical relationship. Each given power controller is arranged to implement a power mode transition policy in order to control transition of the associated power domain between the plurality of power modes.

Abstract: A system and method are provided for controlling a reset procedure. The system has a plurality of power domains, where each power domain comprises a plurality of components, and a plurality of power controllers, wherein each power controller has at last one associated power domain and is arranged to control a supply of power to each associated power domain. The plurality of power controllers are arranged in a hierarchical arrangement comprising two or more hierarchical levels. A given power controller at a given hierarchical level is arranged to implement a reset procedure requiring a reset to be performed in a given reset domain, where the given reset domain comprises at least a subset of the components provided in multiple power domains associated with multiple power controllers provided in at least one hierarchical level below the given hierarchical level.

Abstract: An integrated circuit (2) has first and second domains (4). The first domain has a power controller (22) to control the power state of at least one device (20) in the second domain based on power management signals exchanged on a power management channel (24) between the first and second domains A reset isolation bridge (40) is provided on the power management channel (24) between the first and second domains (4). The bridge (40) has first and second interfaces (42, 44) to exchange the power management signals with the first and second domains respectively. Isolating circuitry (46) is provided in the bridge (40) to respond to a reset indication (8) indicating reset of one of the first and second domains, to isolate state transitions of the power management signals at the first and second interfaces (42, 44) from each other.

Abstract: An integrated circuit (2) has first and second domains (4). The first omain has a power controller (22) to control the power state of at least one device (20) in the second domain based on power management signals exchanged on a power management channel (24) between the first and second domains A reset isolation bridge (40) is provided on the power management channel (24) between the first and second domains (4). The bridge (40) has first and second interfaces (42, 44) to exchange the power management signals with the first and second domains respectively. Isolating circuitry (46) is provided in the bridge (40) to respond to a reset indication (8) indicating reset of one of the first and second domains, to isolate state transitions of the power management signals at the first and second interfaces (42, 44) from each other.

Abstract: A data processing system includes interconnect circuitry providing a plurality of memory transaction paths between one or more transaction masters, including a processor, debugging circuitry and a DMA unit, and one or more transaction slaves including a non-volatile memory, a DRAM memory and an I/O interface. A cache memory is provided between the interconnect circuitry and the non-volatile memory. This cache memory may be a two way set associative cache memory. The cache memory may serve as a read-only cache memory. A cache miss will result in a line fill of a cache line including the target data which was missed. If prefetching is enabled for the cache memory and the transaction was attempting to read a program instruction, then a prefetch operation may be performed in which a further contiguous cache line of data is also fetched into the cache memory upon the cache miss.

Abstract: A data processing apparatus 2 includes a plurality of power domains controlled by respective power control signals PCS. Power control circuitry 22 includes mapping circuitry which maps a plurality of power status signals PSS indicative of the power status of respective power domains, and received from those power domains, to form the power control signals which are then supplied power domains. The mapping circuitry may be controlled by mapping parameters stored within a memory mapped array. The mapping parameters may specify that a given power control signal is either sensitive or insensitive to the power status of a particular other power domain within the data processing apparatus 2. The mapping parameters may be fixed or software programmable.

Abstract: A data processing system 2 includes interconnect circuitry 10 providing a plurality of memory transaction paths between one or more transaction masters, including a processor 4, debugging circuitry 6 and a DMA unit 8, and one or more transaction slaves including a non-volatile memory 12, a DRAM memory 18 and an I/O interface 20. A cache memory 26 is provided between the interconnect circuitry 10 and the non-volatile memory 12. This cache memory 26 may be a two way set associative cache memory. The cache memory 26 may serve as a read-only cache memory. A cache miss will result in a line fill of a cache line including the target data which was missed. If prefetching is enabled for the cache memory 26 and the transaction was attempting to read a program instruction, then a prefetch operation may be performed in which a further contiguous cache line of data is also fetched into the cache memory 26 upon the cache miss.