Patents by Inventor Gerhard Beitel
Gerhard Beitel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090011556Abstract: A method for producing a microelectronic structure is suggested in which a layer structure (30) which partially covers a substrate (5) and which comprises at least one first conductive layer (15,20) which reaches to a side wall (35) of the layer structure (30), is covered with a second conductive layer (45). The second conductive layer (45) is then subsequently back-etched to as great an extent as possible with an etching process with physical delamination, wherein delaminated material deposits on the side wall (35) of the layer structure (30). On the side wall (35) the delaminated material forms a protection layer (60) by means of which the first conductive layer (15,20) is to be protected from attack by oxygen to the furthest extent possible.Type: ApplicationFiled: September 5, 2001Publication date: January 8, 2009Inventors: Gerhard Beitel, Wolfgang Hoenlein, Reinhard Stengl, Elke Fritsch, Siegfried Schwarzl, Hermann Wendt
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Patent number: 7078309Abstract: The invention provides methods which can be used to structure even precious metal electrodes with conventional CMP steps, in particular with the aid of conventional slurries such as are already used to structure non-precious metals. Owing to the formation of an alloy, the chemically active components of the slurry are capable of attacking the additive to the precious metal in the alloy, as a result of which the surface of the alloy layer is roughened and the mechanical removal of the precious metal is increased.Type: GrantFiled: December 11, 2000Date of Patent: July 18, 2006Assignee: Infineon Technologies AGInventors: Gerhard Beitel, Annette Sänger, Walter Hartner
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Patent number: 7042705Abstract: The present invention provides a sidewall oxygen diffusion barrier and a method for fabricating the sidewall oxygen diffusion barrier that reduces the diffusion of oxygen into contact plugs during a CW hole reactive ion etch of a ferroelectric capacitor of an FeRAM device. In one embodiment the sidewall barrier is formed from a substrate fence. In another embodiment, the sidewall barrier is formed by etching back an oxygen barrier.Type: GrantFiled: January 30, 2003Date of Patent: May 9, 2006Assignees: Infineon Technologies AG, Kabushiki Kaisha ToshibaInventors: Haoren Zhuang, Ulrich Egger, Kazuhiro Tomioka, Jingyu Lian, Nicolas Nagel, Andreas Hilliger, Gerhard Beitel
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Patent number: 7031138Abstract: In a capacitor and a method for its manufacture, a first electrode layer and a second electrode layer are formed such that a ferroelectric layer is situated between the first and second electrode layer. A first bilayer or multi-layer seed structure is formed between the ferroelectric layer and either the first electrode layer or the second electrode layer.Type: GrantFiled: December 9, 2002Date of Patent: April 18, 2006Assignees: Infineon Technologies AG, Kabushiki Kaisha ToshibaInventors: Bum-Ki Moon, Gerhard Beitel, Osamu Arisumi, Hiroshi Itokawa
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Patent number: 7009230Abstract: An improved barrier stack for inhibiting diffusion of atoms or molecules, such as O2 is disclosed. The barrier stack is particularly useful in capacitor over plug structures to prevent plug oxidation which can adversely impact the reliability of the structures. The barrier stack includes first and second barrier layers. In one embodiment, the first barrier layer comprises first and second sub-barrier layers having mismatched grain boundaries. The sub-barrier layers are selected from, for example, Ir, Ru, Pd, Rh, or alloys thereof. By providing mismatched grain boundaries, the interface of the sub-barrier layers block the diffusion path of oxygen. To further enhance the barrier properties, the first barrier layer is passivated with O2 using, for example, a rapid thermal oxidation. The RTO forms a thin oxide layer on the surface of the first barrier layer. The oxide layer can advantageously promote mismatching of the grain boundaries of the first and second sub-barrier layer.Type: GrantFiled: July 10, 2003Date of Patent: March 7, 2006Assignees: Infineon Technologies Aktiengesellschaft, Kabushiki Kaisha ToshibaInventors: Bum Ki Moon, Gerhard Beitel, Nicolas Nagel, Andreas Hilliger, Koji Yamakawa, Keitaro Imai
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Publication number: 20050127421Abstract: A semiconductor module is described which is essentially constructed from a silicon material and has an insulation layer for example in the form of a gate insulation layer or a MOS transistor or in the form of an insulation layer of a memory cell for a dynamic memory module. The insulation layer preferably comprises a dielectric material whose band gap is greater than the band gap of SiO2. To construct the insulation layer, use is made of materials which have a metal-fluorine compound, such as e.g. lithium fluoride. Particularly thin insulation layers are provided by the material described.Type: ApplicationFiled: January 16, 2003Publication date: June 16, 2005Applicant: Infineon Technologies AGInventors: Harald Seidl, Jorn Lutzen, Gerhard Beitel, Thomas Hecht, Annette Sanger, Albert Birner
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Patent number: 6897501Abstract: A capacitor structure having a capacitor with a top electrode, a bottom electrode, and a capacitor dielectric layer between the top and bottom electrodes is disclosed. The capacitor includes upper and lower portions. The demarcation between the upper and lower portion is located between top and bottom surfaces of the capacitor dielectric layer. A dielectric layer is provided on the sidewalls of the upper portion of the capacitor to prevent shorting between the electrodes that can be caused by a conductive fence formed during processing.Type: GrantFiled: February 28, 2003Date of Patent: May 24, 2005Assignee: Infineon Technologies AktiengesellschaftInventors: Haoren Zhuang, Ulrich Egger, Jingyu Lian, Gerhard Beitel, Karl Hornik
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Patent number: 6891713Abstract: Reduced degradation to capacitor properties is disclosed. A hydrogen storage layer is provided over at least a portion a top capacitor electrode. The hydrogen storage layer absorbs and stores hydrogen, preventing hydrogen from diffusing to the capacitor. The hydrogen storage layer has, for example, lanthium nitride, titanium zirconium nitride, amorphous sm—co, nanostructured carbon, or a combination thereof.Type: GrantFiled: June 13, 2003Date of Patent: May 10, 2005Assignee: Infineon Technologies AktiengesellschaftInventors: Bum Ki Moon, Gerhard Beitel
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Patent number: 6825116Abstract: A method for removing structures from a substrate is described. The method includes providing a substrate that has the structures that must be removed, applying a sacrifice layer, and removing the structures and the sacrifice layer in a polishing step. The method has the advantage that the sacrifice layer surrounds the structures that must be removed and stabilizes them, so that the structures can be eroded slowly and successively in the subsequent polishing step without breaking off. This prevents a smearing of the material of the structures such as occurs given direct polishing without a sacrifice layer.Type: GrantFiled: April 30, 2001Date of Patent: November 30, 2004Assignee: Infineon Technologies AGInventors: Gerhard Beitel, Mattias Ahlstedt, Walter Hartner, Günther Schindler, Marcus Kastner, Volker Weinrich
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Patent number: 6821187Abstract: The invention discloses a method for the chemical-mechanical polishing of layers composed of metals of the group of platinum metals, particularly iridium. In the CMP process, high erosion rates for iridium and a high selectivity relative to silicon oxide are achieved upon employment of a polishing fluid that contains 1 through 6% by weight abrasive particles, 2 through 20% by weight of at least one oxidation agent selected from the group comprising Ce(IV) salts, salts of chloric acid, salts of peroxodisulfuric acid, hydrogen peroxide and salts of hydrogen peroxide, and 74 through 97% by weight water. This enables the structuring of iridium layers with the assistance of an oxide mask and a CMP process.Type: GrantFiled: October 15, 2002Date of Patent: November 23, 2004Assignee: Infineon Technologies AGInventors: Gerhard Beitel, Annette Saenger, Gerd Mainka, Rainer Florian Schnabel
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Publication number: 20040178431Abstract: An improved barrier stack for inhibiting diffusion of atoms or molecules, such as O2 is disclosed. The barrier stack is particularly useful in capacitor over plug structures to prevent plug oxidation which can adversely impact the reliability of the structures. The barrier stack includes first and second barrier layers. In one embodiment, the first barrier layer comprises first and second sub-barrier layers having mismatched grain boundaries. The sub-barrier layers are selected from, for example, Ir, Ru, Pd, Rh, or alloys thereof. By providing mismatched grain boundaries, the interface of the sub-barrier layers block the diffusion path of oxygen. To further enhance the barrier properties, the first barrier layer is passivated with O2 using, for example, a rapid thermal oxidation. The RTO forms a thin oxide layer on the surface of the first barrier layer. The oxide layer can advantageously promote mismatching of the grain boundaries of the first and second sub-barrier layer.Type: ApplicationFiled: July 10, 2003Publication date: September 16, 2004Inventors: Bum Ki Moon, Gerhard Beitel, Nicolas Nagel, Andreas Hilliger, Koji Yamakawa, Keitaro Imai
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Publication number: 20040171274Abstract: In semiconductor device fabrication processes which include the formation of hardmask elements 17 including Al2O2, unwanted Al2O3 is left between the hardmask elements 17. The unwanted Al2O3 includes a layer 9 of Al2O3which is not homogenous across the surface of the structure 3 it overlies, and Al2O3 deposits on the sides of the hardmask elements 17. A method is proposed in which any such unwanted Al2O3 between the hardmask elements 17 is removed by a wet etching step in which the unwanted Al2O3 is exposed to an etchant liquid which etches the Al2O3 at a faster rate than other portions of the structure. This step allows the unwanted Al2O3 to be removed substantially completely without causing significant detriment to those other portions of the structure. Subsequently, an RIE etching step can be performed using the hardmask elements 17 as a mask, without the unwanted Al2O3 obstructing the RIE etching step.Type: ApplicationFiled: February 27, 2003Publication date: September 2, 2004Inventors: Haoren Zhuang, Ulrich Egger, Uwe Wellhausen, Rainer Bruchhaus, Karl Hornik, Jingyu Lian, Gerhard Beitel, Kazuhiro Tomioka, Katsuki Natori
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Publication number: 20040171252Abstract: An improved method of reducing contamination in processing of ICs is disclosed. The method includes forming a contamination protection layer on at least the back surface of the substrate. The contamination protection layer comprises a low diffusion factor and can be cleaned efficiently. In one embodiment, the contamination protection layer comprises HCD silicon nitride.Type: ApplicationFiled: February 28, 2003Publication date: September 2, 2004Inventors: Haoren Zhuang, Katsuaki Natori, Gerhard Beitel, Bum-ki Moon, Moto Yabuki, Yoshitaka Tsunashima, Karl Hornik
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Publication number: 20040169211Abstract: A capacitor structure having a capacitor with a top electrode, a bottom electrode, and a capacitor dielectric layer between the top and bottom electrodes is disclosed. The capacitor comprises an upper and lower portion. The demarcation between the upper and lower portion is located between top and bottom surfaces of the capacitor dielectric layer. A dielectric layer is provided on the sidewalls of the upper portion of the capacitor to prevent shorting between the electrodes that can be caused by a conductive fence formed during processing.Type: ApplicationFiled: February 28, 2003Publication date: September 2, 2004Inventors: Haoren Zhuang, Ulrich Egger, Jingyu Lian, Gerhard Beitel, Karl Hornik
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Publication number: 20040149477Abstract: The present invention provides a sidewall oxygen diffusion barrier and method for fabricating the sidewall oxygen diffusion barrier to reduce the diffusion of oxygen to contact plugs during CW hole reactive ion etch processing of a ferroelectric capacitor of an FeRAM device. In one embodiment the sidewall barrier is formed from a substrate fence, while in another embodiment the sidewall barrier is formed by etching back an oxygen barrier.Type: ApplicationFiled: January 30, 2003Publication date: August 5, 2004Inventors: Haoren Zhuang, Ulrich Egger, Kazuhiro Tomioka, Jingyu Lian, Nicolas Nagel, Andreas Hilliger, Gerhard Beitel
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Publication number: 20040109280Abstract: In a capacitor and a method for its manufacture, a first electrode layer and a second electrode layer are formed such that a ferroelectric layer is situated between the first and second electrode layer.Type: ApplicationFiled: December 9, 2002Publication date: June 10, 2004Inventors: Bum-Ki Moon, Gerhard Beitel, Osamu Arisumi, Hiroshi Itokawa
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Publication number: 20040057193Abstract: Reduced degradation to capacitor properties is disclosed. A hydrogen storage layer is provided over at least a portion a top capacitor electrode. The hydrogen storage layer absorbs and stores hydrogen, preventing hydrogen from diffusing to the capacitor. The hydrogen storage layer comprises, for example, lanthium nitride, titanium zirconium nitride, amorphous sm—co, nanostructured carbon, or a combination thereof.Type: ApplicationFiled: June 13, 2003Publication date: March 25, 2004Inventors: Bum Ki Moon, Gerhard Beitel
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Patent number: 6686265Abstract: A capacitor electrode is produced with an underlying barrier structure. A barrier incorporation layer is used and a CMP (chemical mechanical polishing) process is employed in order to produce the barrier structure. The capacitor electrode with an underlying barrier structure is produced by depositing a barrier layer on a semiconductor substrate; forming a barrier structure from the barrier layer with a lithographic mask and an etching step; depositing a barrier incorporation layer covering the barrier structure and surrounding regions; and removing the barrier incorporation layer with chemical mechanical polishing until the barrier structure is uncovered, to thereby form the capacitor electrode above the barrier structure.Type: GrantFiled: April 22, 2002Date of Patent: February 3, 2004Assignee: Infineon Technologies AGInventors: Gerhard Beitel, Annette Sänger, Igor Kasko
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Patent number: 6621683Abstract: A capacitor with improved reliability is disclosed. The capacitor includes a bottom electrode, a top electrode, and an intermediate layer therebetween. A contact, which is electrically coupled to the top electrode, is provided. At least a portion of the contact is offset from the capacitor. By offsetting the contact from the top electrode, the etch damage to the top electrode is reduced, thereby reducing or eliminating the need for the anneal to repair the etch damage.Type: GrantFiled: September 19, 2002Date of Patent: September 16, 2003Assignee: Infineon Technologies AktiengesellschaftInventors: Bum-ki Moon, Andreas Hilliger, Nicolas Nagel, Gerhard Beitel
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Patent number: 6614642Abstract: A capacitor over plug (COP) structure is disclosed. The COP avoids the step which is created in conventional COP structures, which adversely impacts the properties of the capacitor. In one embodiment, the step is avoided by providing a plug having upper and lower portions. The upper portion, which is coupled to the bottom electrode of the capacitor, has substantially the same surface area as the bottom electrode. A barrier layer can be provided between the plug and bottom electrode to avoid oxidation of the plug material.Type: GrantFiled: September 19, 2002Date of Patent: September 2, 2003Assignees: Infineon Technologies Aktiengesellschaft, Kabushiki Kaisha ToshibaInventors: Bum-ki Moon, Moto Yabuki, Gerhard Beitel, Nicolas Nagel, Andreas Hilliger, Takamichi Tsuchiya