Abstract: A semiconductor memory is fabricated with a vertical transistor situated in an upper section of a trench above a trench capacitor. First, an auxiliary insulation layer is applied to the conductive material of an inner electrode or to a connecting material of the trench capacitor. The connecting material is situated on the inner electrode, so that, during an epitaxial deposition, semiconductor material grows only on the uncovered sidewalls in the upper section of the trench. A nitride layer, is deposited conformally and the residual cavity between the inner electrode and the epitaxial semiconductor layer is filled with a doped further conductive material. The nitride layer isolates the epitaxial semiconductor layer from the further conductive material, so that no crystal lattice defects can propagate from there into the epitaxial semiconductor layer. Dopants are outdiffused from the further conductive material into the epitaxial semiconductor layer to form a doping region.

Abstract: The memory cell according to the invention has a vertical selection transistor, via whose channel region the inner electrode of the trench capacitor can be connected to a bit line. The channel region is led to the bit line through an associated word line, which completely or partially encloses the channel region. As a result, a conductive channel can be formed within the channel region depending on the potential of the word line. Preferably, the extent of the trench hole in the word line direction is at least 1.5 times as large as in the bit line direction.

Abstract: The present invention relates to a method for producing a vertical transistor, and to a vertical transistor. A sacrificial gate oxide and a sacrificial gate electrode are used during the production of the vertical transistor to makes it possible to considerably reduce or entirely avoid negative effects that normally result from the production of insulation structures between the vertical transistors. In particular, broadening of the gate oxide at the edge of the gate electrode can be prevented, and the edge of the gate electrode can be influenced deliberately. This allows vertical transistors to be produced having a current/voltage characteristic that can be adjusted specifically. In particular, vertical transistors can be produced having a pronounced corner effect.

Abstract: The memory cell according to the invention has a vertical selection transistor, via whose channel region the inner electrode of the trench capacitor can be connected to a bit line. The large extent of the channel region in the bit line direction means that the trench capacitor can be rapidly charged and read. The channel region is led to the bit line through an associated word line, which completely or partially encloses the channel region. A conductive channel can be formed within the channel region depending on the potential of the word line.

Abstract: A trench cell for use in a DRAM array includes a vertical selection transistor of a first conductivity type at the—seen in the bit line direction—first side of the trench hole, a blocking doping region near the surface, of a second conductivity type, is provided adjacent to the trench hole, the blocking doping region lying opposite the vertical selection transistor. As a result, leakage currents can be avoided and, in addition, the trench cells can be disposed at a shorter distance from one another.

Abstract: A semiconductor memory having memory cells, each memory cell includes a selection transistor and a trench capacitor. The selection transistor is formed in the form of a vertical transistor. In such a case, two word lines are separated only by a connecting channel that enables an electrically conductive connection between a trench filling of the trench capacitor and a bit line.

Abstract: A method for processing a substrate to produce a structure, for example an insulating trench, uses a lithographic mask exposure process. Conventionally, the optical resolution limit prescribes the minimum width for any structure that can be produced. The method produces structures having a width less than the optical resolution limit on raised regions of the semiconductor substrate. Use is made of spacer technology, before the application of which the method first involves the local level ratios on the semiconductor substrate being reversed by trench etching, trench filling and subsequent back-etching of the trench interspace. The method allows insulating trenches of any narrow width between zero and the respective optical resolution limit to be produced on locally raised surface regions of the substrate.

Abstract: Capacitor devices are formed in an essentially vertically extending fashion in order to achieve an essentially three-dimensional configuration or a configuration extending into the third dimension. A contacting of plug regions is performed after producing the capacitor devices. Such capacitor devices provide an increased integration density in a semiconductor memory device.

Abstract: A method of fabricating semiconductor memory devices is simplified by providing at least some plug regions, which are provided for contacting storage capacitor devices of a capacitor configuration, such that the plug regions have in each case a region that is elevated above the surface region of a passivation region.

Abstract: To achieve a highest possible integration density in a semiconductor memory device having storage capacitors as storage elements, the method according to the invention forms the capacitor devices in substantially vertically extending fashion, to, as a result, achieve a substantially three-dimensional configuration and an configuration extending into the third dimension for the capacitor devices, a contact connection of the storage capacitors being formed after the production of the storage capacitors.

Abstract: To manufacture FeRAM memories in a particularly space-saving fashion and, thus, increase the storage density, a manufacturing method forms at least some of the multiplicity of capacitor devices used as storage elements with a multiplicity of individual capacitors that are connected in parallel with one another. The individual capacitors have ferroelectric or paraelectric dielectric regions with different coercitive voltages such that there is a resulting multiplicity of storage states for each of the individual capacitors.

Abstract: A semiconductor body-having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells.

Abstract: A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells.

Abstract: A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells.

Abstract: A trench capacitor having a substrate with a trench extending therein with a nested, e.g., concentric, conductive regions disposed within the trench. A dielectric material is disposed within the substrate. The dielectric material has portions thereof disposed between the concentric conductive regions to dielectrically electrically separate one of the conductive regions from another one of the conductive regions. The dielectrically separated conductive regions provide a pair of electrodes for the capacitor. Selected ones of the concentric conductive regions are electrically connected to provide one of the electrodes for the capacitor. The substrate has a conductive region therein and one of the concentric conductive regions providing one of the electrodes is electrically connected to the conductive region in the substrate. One of the concentric conductive regions is electrically connected to a conductive region in the substrate through a bottom portion of the trench.

Abstract: A DRAM cell is disposed in an electrically isolated region of a semiconductor body. The cell includes a storage capacitor disposed in a trench. The capacitor is disposed entirely within the isolated region of the semiconductor body. The cell includes a transistor disposed in the isolated region. The transistor has a pair of gates. A word line is provided for addressing the cell. The word line has an electrical contact region to the transistor. The word line contact region is disposed entirely within the isolated region of the semiconductor body. The transistor has an active area. The active area has source, drain, and channel regions. The active area is disposed entirely within the isolated region of the semiconductor body. A bit line is provided for the cell. The bit line is in electrical contact with the gates of the transistor at a pair of bit line contact regions. Both such bit line contact regions are disposed entirely within the isolated region of the cell.

Abstract: A method for manufacturing VLSI MOS-transistor circuits involving the production of transistors by means of a spacer layer technique and ohmic contacts from the gate interconnect to the diffused regions of the substrate (thus providing buried contacts) both being simultaneously generated. Contact holes are provided at the desired location in the substrate before the deposition of the spacer layer occurs across the surface of the substrate. The spacer layer is simultaneously structured at the side walls of the gates and at the side walls of the interconnects which serve as connections. The contact hole region is doped at the same time as the source/drain areas are provided by ion implantation. The combined manufacture of transistors using spacer technology and buried contacts makes it possible to manufacture MOS logic circuits and memory circuits with voltage stable transistors in high packing density.